Enhanced timing-based transition delay testing for small delay defects

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 336-342

  Putman, Richard ^a   Gawde, Rahul ^a  

^a Cirrus Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY DEFECTS; STANDARD STATIC TIMING ANALYSIS (STA);

DEFECTS; ELECTRIC NETWORK ANALYSIS; SYSTEMS ANALYSIS;

DELAY CIRCUITS;

EID: 33751085673     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.33     Document Type: Conference Paper

References (13)

1. Datta, R., R. Gupta, A. Sebastine and J.A. Abraham and M. d'Abreu, "Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing," International Test Conference, pp. 1118-1127, Oct. 2004.
2. Yan, H., and A. Singh, "Experiments in Detecting Delay Faults Using Multiple Higher Frequency Clocks and Results from Neighboring Die," International Test Conference, pp. 105-111, Oct. 2003.
3. Madge, R., B. Benware and W.R. Daasch, "Obtaining High Defect Coverage for Frequency Dependent Defects in Complex ASICs," IEEE Design & Test of Computers, pp. 46-53, Sept-Oct 2003.
4. Crouch, A., J. Potter and J. Doege, "AC Scan Path Selection for Physical Debugging," IEEE Design & Test of Computers, pp.34-40, Sept-Oct 2003.
5. Waicukauski, J., E. Lindbloom, B. Rosen and V. Iyengar, "Transition Fault Simulation," IEEE Design & Test of Computers, pp. 32-38, April 1987.
6. Smith, O., "Model for Delay Faults Based Upon Paths," International Test Conference, pp-342-349, Nov. 1985.
7. Lin, C., and S. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. on CAD, vol. 6, pp. 694-703, Sept. 1987.
8. Kruseman, B., A. Mahji, G. Gronthoud and S. Eichenberger, "On Hazard-Free Patterns for Fine-Delay Fault Testing," International Test Conference, pp. 213-222, Oct. 2004.
9. th VLSI Test Symposium, 1996.
10. th VLSI Test Symposium, 2000.
11. Pomeranz, I., and S. Reddy, "Design-for-Testability for Path Delay Faults in Large Combinational Circuits Using Test Points," IEEE Trans. on CAD, vol. 17, pp. 333-343, Apr. 1998.
12. Gupta, P., and M. Hsiao, "ALAPTF: A New Transition Fault Model and the ATPG Algorithm," International Test Conference, pp. 1053-1060, Oct. 2004.
13. Li, W., et al., "On Path Selection in Combinational Logic Circuits," IEEE Trans. on CAD, vol. 8, pp. 56-63, Jan. 1989.