A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 216-217

  Hu, Jason ^a   Dolev, Noam ^a   Murmann, Boris ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

CMOS; Pipelined ADC; Source follower and dynamic amplifier; Switched capacitor circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOW POWER ELECTRONICS; OPERATIONAL AMPLIFIERS; VLSI CIRCUITS;

90-NM CMOS; GAIN STAGES; PIPELINED ADCS; RESIDUE AMPLIFICATION; SOURCE FOLLOWER AND DYNAMIC AMPLIFIER; SOURCE FOLLOWERS; SWITCHED -CAPACITOR CIRCUITS; ULTRA LOW POWER;

PIPELINES;

EID: 51949099980     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4586012     Document Type: Conference Paper

References (3)

1. M. A. Copeland and J. M. Rabaey, "Dynamic amplifier for m.o.s. technology," Electron. Lett., vol. 15, pp. 301-302, May 1979.
2. S. Ranganathan and Y. Tsividis, "Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results," IEEE J. Solid-State Circuits, vol. 38, pp. 2087-2093, Dec 2003.
3. A. N. Karanicolas, H.-S. Lee and K. L. Barcrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, Dec 1993