A 150MS/S 133μW 7b ADC in 90nm digital CMOS using a comparator-based asynchronous binary-search sub-ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 242-244

  Van Der Plas, Geert ^a   Verbruggen, Bob ^a,b  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL); ENERGY EFFICIENCY;

BINARY SEARCH; DIGITAL CMOS; NYQUIST BAND; PROTOTYPE IMPLEMENTATIONS;

COMPARATOR CIRCUITS;

EID: 49549103790     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523147     Document Type: Conference Paper

References (6)

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2. G. Van der Plas, S. Decoutere and S. Donnay, "A 0.16pF/conversion- step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process," ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.
3. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993.
4. B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul. 2004.
5. P. Nuzzo, F De Bernardinis, P. Terreni, and G.Van der Plas, "Efficient Calibration Through Statistical Behavioral Modeling of a High-Speed Low-Power ADC," Proc. of PRIME, pp. 297-300, Jun. 2006.
6. S. Chen and R. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 574-575, Feb. 2006.