A 1.9μW 4.4fJ/conversion-step 10b 1MS/S charge-redistribution ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 244-246

  Van Elzakker, Michiel ^a,b   Van Tuijl, Ed ^a,c   Geraedts, Paul ^a   Schinkel, Daniel ^a,c   Klumperink, Eric ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c Axiom IC Twente   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

SOLID STATE DEVICES;

CHARGE REDISTRIBUTION; CHARGE REDISTRIBUTION DAC; SAMPLE RATE; SAR ADC;

NETWORKS (CIRCUITS);

EID: 49549109409     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523148     Document Type: Conference Paper

References (4)

1. J. McCreary and P. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques," IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
2. B. Ginsburg and A. Chandrakasan, "An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC," Proc. IEEE ISCAS, vol. 1, pp. 184-187, May 2005.
3. D. Schinkel, E. Mensink, E. Klumperink, et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2007.
4. J. Craninckx and G. van der Plas, "A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007.