A double-tail latch-type voltage sense amplifier with 18ps setup+hold time

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages

  Schinkel, Daniël ^a   Mensink, Eisse ^a   Klumperink, Eric ^a   Van Tuijl, Ed ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL;

CROSS-COUPLED STAGE; INPUT EQUIVALENT NOISE; LATCH-TYPE VOLTAGE SENSE AMPLIFIER;

AMPLIFIERS (ELECTRONIC);

EID: 34548852188     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373420     Document Type: Conference Paper

References (5)

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2. D. Schinkel et al., "A 3Gb/s/ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects," IEEE J. Solid-State Circuits, pp. 297-306, Jan., 2006.
3. B. Nikolic et al., "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements," IEEE J. Solid-State Circuits, pp. 876-884, June, 2000.
4. B. Wicht et al., "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier," IEEE J. Solid-State Circuits, pp. 1148-1158, July, 2004.
5. K.-L.J. Wong and C.-K.K. Yang, "Offset Compensation in Comparators with Minimum Input-Referred Supply Noise," IEEE J. Solid-State Circuits, pp. 837-840, May, 2004.