Software assisted digital RF processor (DRP) for single-chip GSM radio in 90 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 2, 2010, Pages 276-288

  Staszewski, Roman ^a   Staszewski, Robert Bogdan ^b   Jung, Tom ^a   Murphy, Thomas ^a   Bashir, Imran ^a   Eliezer, Oren ^a   Muhammad, Khurram ^a   Entezari, Mitch ^a  

^a TEXAS INSTRUMENTS   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

All digital phase locked loop (ADPLL); Application programming interface (API); Built in self test (BIST); Calibration; Compensation; Digital processor; Digitally assisted analog; Digitally controlled oscillator (DCO); Mobile phones; Nanometer scale CMOS; RF

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL); BUILT-IN SELF-TEST (BIST); CMOS RF; DIGITAL PROCESSOR; DIGITAL PROCESSORS; DIGITALLY CONTROLLED OSCILLATORS; NANO-METER SCALE;

ANALOG CIRCUITS; BUILT-IN SELF TEST; CALIBRATION; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; DIGITAL CONTROL SYSTEMS; DIGITAL RADIO; MICROPROCESSOR CHIPS; MOBILE DEVICES; MOBILE PHONES; PHASE INTERFACES; PHASE LOCKED LOOPS; SPACE OPTICS; SPURIOUS SIGNAL NOISE; TELEPHONE; TELEPHONE SETS;

APPLICATION PROGRAMMING INTERFACES (API);

EID: 76849101970     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2036763     Document Type: Article

References (35)

1. K. Muhammad, R. B. Staszewski, and D. Leipold, "Digital RF processing: Toward low-cost reconfigurable radios," IEEE Commun.Mag., vol.43, no.8, pp. 105-113, Aug. 2005. (Pubitemid 41300921)
2. R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de-Obaldia, and P. T. Balsara, "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2278-2291, Dec. 2004.
3. R. B. Staszewski, D. Leipold, O. Eliezer, M. Entezari, K. Muhammad, I. Bashir, C.-M. Hung, J.Wallberg, R. Staszewski, P. Cruise, S. Rezeq, S. Vemulapalli, K. Waheed, N. Barton, M.-C. Lee, C. Fernando, K. Maggio, T. Jung, I. Elahi, S. Larson, T. Murphy, G. Feygin, I. Deng, T. Mayhugh, Y.-C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, J.Mehta, S. Glock, T. Almholt, and S. Bhatara, "A 24mm quad-band single-chip GSM radio with transmitter calibration in 90 nm digital CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, vol.607, pp. 208-209, sec. 10.5.
4. R. B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All-digital PLL and transmitter for mobile phones," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2469-2482, Dec. 2005.
5. K. Muhammad, Y.-C. Ho, T. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, "The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process," IEEE J. Solid-State Circuits, vol.41, no.8, pp. 1772-1783, Aug. 2006.
6. A. A. Abidi, "RF CMOS comes of age," IEEE J. Solid-State Circuits, vol.39, no.4, pp. 549-561, Apr. 2004.
7. P. H. Bonnaud et al., "A fully integrated SoC for GSM/GPRS in 0.13 μmCMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, vol.667, pp. 482-483.
8. S. Mehta et al., "A 1.9 GHz single-chip CMOS PHS cellphone," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, vol.668, pp. 484-485.
9. F. O. Eynde et al., "A fully-integrated single-chip SOC for Bluetooth," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, vol.446, pp. 196-197, sec. 13.1.
10. D.Weber,W. Si, S. Abdollahi-Alibeik, M.-L. Lee, R. Chang, H. Dogan, S. Luschas, and P. Husted, "A single-chip CMOS radio SoC for v2.1 Bluetooth applications," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, vol.620, pp. 364-365, sec. 20.5.
11. L. Nathawad et al., "A dual-band CMOS MIMO radio SoC for IEEE 802.11n wireless LAN," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, vol.619, pp. 358-359, sec. 20.2.
12. O. Eliezer, I. Bashir, R. B. Staszewski, and P. T. Balsara, "Built-in self testing of a DRP-based GSM transmitter," in Proc. 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2007, pp. 339-342, sec. RMO4D-2. (Pubitemid 47486683)
13. R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, "A first multigigahertz digitally controlled oscillator for wireless applications," IEEE Trans. Microw. Theory Tech., vol.51, no.11, pp. 2154-2164, Nov. 2003.
14. R. B. Staszewski, D. Leipold, and P. T. Balsara, "Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.50, no.11, pp. 887-892, Nov. 2003.
15. A. D. Berny, A. M. Niknejad, and R. G. Meyer, "A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration," IEEE J. Solid-State Circuits, vol.40, no.4, pp. 909-917, Apr. 2005.
16. K. Dufrene and R. Weigel, "A novel IP2 calibration method for lowvoltage downconversion mixers," in Proc. 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2006.
17. T. Das, A. Gopalan, C.Washburn, and P. R. Mukund, "Self-calibration of input-match in RF front-end circuitry," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol.52, no.12, pp. 821-825, Dec. 2005.
18. Y.-H. Hsieh et al., "An auto-I/Q calibrated CMOS transceiver for 802. 11g," IEEE J. Solid-State Circuits, vol.40, no.11, pp. 2187-2192, Nov. 2005.
19. R. Bagheri, A. Mirzaei, S. Chehrazi, M. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. Abidi, "An 800 MHz to 5 GHz software-defined radio receiver in 90nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, vol.667, pp. 480-481.
20. J. Craninckx, M. Liu, D. Hauspie, V. Giannini, T. Kim, J. Lee, M. Libois, B. Debaillie, C. Soens, M. Ingels, A. Baschirotto, J. Van Driessche, L. Van der Perre, and P. Vanbekbergen, "A fully reconfigurable software-defined radio transceiver in 0.13 μm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, vol.607, pp. 346-347.
21. J.-C. Lin, "A low-phase-noise 0.004-ppm/step DCXO with guaranteed monotonicity in the 90-nm CMOS process," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2726-2734, Dec. 2005.
22. R. B. Staszewski, I. Bashir, and O. Eliezer, "RF built-in self test of a wireless transmitter," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol.54, no.2, pp. 186-190, Feb. 2007. (Pubitemid 46477687)
23. GSM Specification: Radio Transmission and Reception, GSM 05.05 Version 8.5.1, ETSI EN 300 910, Nov. 2000 [Online]. Available: http:// www.etsi.org
24. R. Staszewski, T. Jung, R. B. Staszewski, K. Muhammad, D. Leipold, T. Murphy, S. Sabin, J. Wallberg, S. Larson, M. Entezari, J. Fresquez, S. Dondershine, and S. Syed, "Software assisted digital RF processor for single-chip GSM radio in 90 nm CMOS," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2005, pp. 81-84.
25. O. Eliezer, B. Staszewski, I. Bashir, S. Bhatara, and P. T. Balsara, "A phase domain approach for mitigation of self-interference in wireless transceivers," IEEE J. Solid-State Circuits, vol.44, no.5, pp. 1436-1453, May 2009.
26. O. Eliezer, O. Friedman, and R. B. Staszewski, "A built-in tester for modulation noise in a wireless transmitter," in Proc. 5th IEEE Dallas Circuits and Systems Workshop: Design, Application, Integration and Software (DCAS-06), Oct. 2006, pp. 59-62.
27. R. B. Staszewski, S. Vemulapalli, P. Vallur, J.Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol.53, no.3, pp. 220-224, Mar. 2006.
28. U. Vollenbruch, Y. Liu, T. Bauernfeind, T. Pittorino, V. Neubauer, T. Mayer, and L. Maurer, "Requirements for time-to-digital converters in the context of digital-PLL based frequency synthesis and GSM modulation," in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2006, pp. 1817-1820.
29. R. Tonietto, E. Zuffetti, and R. Castello, "A 2 MHz bandwidth low noise RF all digital PLL with 12ps resolution time-to-digital converter," in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2006, pp. 150-153.
30. C.-M. Hsu, M. Z. Strayer, and M. H. Perrott, "A low-noise, wide-BW 3.6 GHz digital Σ-N synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 340-341.
31. B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, "A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 855-863, Apr. 2008.
32. E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, "A 3 GHz fractional all-digital PLL with a 1.8 MHz bandwidth implementing spur reduction techniques," IEEE J. Solid-State Circuits, vol.44, no.3, pp. 824-834, Mar. 2009.
33. M. Lee, M. E. Heidari, and A. A. Abidi, "A low-noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 112-113.
34. J. Tangudu, S. Gunturi, S. Jalan, J. Janardhanan, R. Ganesan, D. Sahu, K. Waheed, J. Wallberg, and R. B. Staszewski, "Quantization noise improvement of time to digital converter (TDC) for ADPLL," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2009, pp. 1020-1023.
35. K. Muhammad, R. B. Staszewski, and C.-M. Hung, "Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver," in IEEE Radio Frequency Integrated Circuits (RFIC) Symp. Dig. Papers, Jun. 2004, pp. 405-408.