RF built-in self test of a wireless transmitter

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 2, 2007, Pages 186-190

  Staszewski, Robert Bogdan ^a   Bashir, Imran ^a   Eliezer, Oren ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

All digital phase locked loop (ADPLL); Bluetooth; built in self test (BIST); deep submicrometer CMOS; digitally controlled oscillator (DCO); Global System for Mobile Communications (GSM); mobile phones; phase error (PHE); phase trajectory error; PLL

Indexed keywords

BLUETOOTH; BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MOBILE PHONES; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; WIRELESS TELECOMMUNICATION SYSTEMS;

ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL); DIGITALLY CONTROLLED OSCILLATOR (DCO); PHASE TRAJECTORY ERROR; WIRELESS TRANSMITTER;

TRANSMITTERS;

EID: 33947583710     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.886202     Document Type: Article

References (12)

1. GSM Specification: Radio Transmission and Reception, GSM 05.05 version 8.5.1, ETSIEN 300 910, Nov. 2000 [Online]. Available: http://www.etsi.org
2. I. Bashir, R. B. Staszewski, O. Eliezer, and E. de-Obaldia, “Built-in self testing (BIST) of RF performance in a system-on-chip (SoC),” in Proc. 2005 IEEE Dallas/CAS Workshop: Architectures, Circuits and Implementation of SoC (DCAS'05), Oct. 2005, pp. 215–218.
3. R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291, Dec. 2004.
4. R. B. Staszewski, J. Wallberg, and S. Rezeq et al., “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, Dec. 2005.
5. C.-C. Chung and C.-Y. Lee, “An all-digital phase-locked loop for high-speed clock generation,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 347–351, Feb. 2003.
6. J. Lin, B. Haroun, and T. Foo, “A PVT tolerant 0.18- to 600-MHz self-calibrated digital PLL in 90-nm CMOS process,” in Proc. IEEE Solid-State Circuits Conf., Feb. 2004, vol. 541, pp. 488–489.
7. M. H. Perrott, R. T. Rex, and Y. Huang, “Digitally synthesized loop filter circuit particularly useful for a phase locked loop,” U.S. Patent 6630 868, Oct. 7, 2003.
8. S. Kim and M. Soma, “An all-digital built-in self-test for high-speed phase-locked loops,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 2, pp. 141–150, Feb. 2001.
9. M. Takamiya, H. Inohara, and M. Mizuno, “On-chip jitter-spectrum-analyzer for high-speed digital designs,” in Proc. IEEE Solid-State Circuits Conf., Feb. 2004, vol. 532, pp. 350–351.
10. D. R. McMahill and C. G. Sodini, “A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated ∑-Δfrequency synthesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 18–26, Jan. 2002.
11. R. B. Staszewski and P. T. Balsara, “Phase-domain all-digital phase-locked loop,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 3, pp. 159–163, Mar. 2005.
12. R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 815–828, Nov. 2003.