A highly digital MDLL-B ased clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 855-863

  Helal, Belal M ^a,b   Straayer, Matthew Z ^a,b   Wei, Gu Yeon ^c   Perrott, Michael H ^b  

^a IEEE

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c HARVARD UNIVERSITY   (United States)

Author keywords

Correlated double sampling; Correlation; Deterministic jitter; First order noise shaping; Gated ring oscillator (GRO); Multiplying delay locked loop (MDLL); Reference spur; Scrambling; Time to digital converter (TDC)

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; JITTER; SAMPLING; SENSITIVITY ANALYSIS; SPURIOUS SIGNAL NOISE; TUNING;

CORRELATED DOUBLE SAMPLING; DETERMINISTIC JITTERS; FIRST-ORDER NOISE SHAPING; GATED RING OSCILLATOR (GRO); MULTIPLYING DELAY-LOCKED LOOP (MDLL); REFERENCE SPUR; SCRAMBLING; TIME TO DIGITAL CONVERTER (TDC);

ELECTRIC CONVERTERS;

EID: 41549140087     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917372     Document Type: Conference Paper

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