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Volumn , Issue , 2009, Pages 1020-1023

Quantization noise improvement of time to digital converter (TDC) for ADPLL

Author keywords

[No Author keywords available]

Indexed keywords

ALL-DIGITAL PLL; CARRIER FREQUENCY; COMMUNICATION APPLICATION; INTEGER NUMBERS; INVERTER DELAY; PHASE ERROR; QUANTIZATION ERRORS; QUANTIZATION NOISE; RADIO FREQUENCIES; REFERENCE FREQUENCY; TIME TO DIGITAL CONVERTERS;

EID: 70350156945     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117932     Document Type: Conference Paper
Times cited : (17)

References (6)
  • 1
    • 10444260492 scopus 로고    scopus 로고
    • Staszewski, R.B., Muhammad, K., Leipold, D., Chih-Ming Hung, Yo-Chuol Ho, Wallberg, J.L., Fernando, C., Maggio, K., Staszewski, R., Jung, T., Jinseok Koh, John, S., Irene Yuanying Deng, Sarda, V., Moreira-Tamayo, O., Mayega, V., Katz, R., Friedman, O., Eliezer, O.E., deObaldia E., Balsara, P.T., All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, Solid-State Circuits, IEEE, 39, Issue 12, Dec. 2004 Page(s):2278-2291
    • Staszewski, R.B., Muhammad, K., Leipold, D., Chih-Ming Hung, Yo-Chuol Ho, Wallberg, J.L., Fernando, C., Maggio, K., Staszewski, R., Jung, T., Jinseok Koh, John, S., Irene Yuanying Deng, Sarda, V., Moreira-Tamayo, O., Mayega, V., Katz, R., Friedman, O., Eliezer, O.E., deObaldia E., Balsara, P.T., "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS", Solid-State Circuits, IEEE, Volume 39, Issue 12, Dec. 2004 Page(s):2278-2291
  • 2
    • 27844587416 scopus 로고    scopus 로고
    • A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones Solid-State Circuits
    • Nov, Pages
    • Staszewski, R.B., Chih-Ming Hung, Barton, N., Meng-Chang Lee, Leipold, D., "A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones" Solid-State Circuits, IEEE Journal, Volume 40, Issue 11, Nov. 2005 Page(s):2203-2211
    • (2005) IEEE Journal , vol.40 , Issue.11 , pp. 2203-2211
    • Staszewski, R.B.1    Ming Hung, C.2    Barton, N.3    Chang Lee, M.4    Leipold, D.5
  • 4
    • 15944399705 scopus 로고    scopus 로고
    • Staszewski, R.B., Balsara, P.T., Phase-domain all-digital phase-locked loop Circuits and Systems II: Express Briefs, IEEE Transactions on 52, Issue 3, March 2005 Page(s):159-163
    • Staszewski, R.B., Balsara, P.T., "Phase-domain all-digital phase-locked loop" Circuits and Systems II: Express Briefs, IEEE Transactions on Volume 52, Issue 3, March 2005 Page(s):159-163
  • 6
    • 17144435893 scopus 로고    scopus 로고
    • A High-resolution CMOS Time-to-Digital Converter utilizing a Vernier Delay Line
    • Feb
    • P. Dudek, S. Szczepanski, and J. Hatfield, "A High-resolution CMOS Time-to-Digital Converter utilizing a Vernier Delay" Line, IEEE J. Solid-State Circuits, vol. 35, pp. 240-247, Feb. 2000
    • (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 240-247
    • Dudek, P.1    Szczepanski, S.2    Hatfield, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.