A first multigigahertz digitally controlled oscillator for wireless applications

IEEE Transactions on Microwave Theory and Techniques

Volumn 51, Issue 11, 2003, Pages 2154-2164

  Bogdan Staszewski, Robert ^a   Hung, Chih Ming ^a   Leipold, Dirk ^a   Balsara, Poras T ^b  

^a TEXAS INSTRUMENTS   (United States)

^b The University of Texas at Dallas   (United States)

Author keywords

CMOS digital integrated circuits (ICs); Digital control; Digitally controlled oscillator (DCO); MOS varactor; Voltage controlled oscillators (VCOs)

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DIGITAL CONTROL SYSTEMS; PHASE LOCKED LOOPS; TRANSCEIVERS; VARACTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

DIGITALLY CONTROLLED OSCILLATOR; FREQUENCY TUNING; PHASE NOISE;

VARIABLE FREQUENCY OSCILLATORS;

EID: 0242573743     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2003.818579     Document Type: Article

References (13)

1. F. M. Gardner, "Charge-pump phase-locked loops," IEEE Trans. Commun., vol. COMM-28, pp. 1849-1858, Nov. 1980.
2. R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, "A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications," in Proc. IEEE Radio Frequency Integrated Circuits Symp., sec. MO4B-2, June 2003, pp. 81-84.
3. H. Brugel and P. F. Driessen, "Variable bandwidth DPLL bit synchronizer with rapid acquisition implemented as a finite state machine," IEEE Trans. Commun., vol. 42, pp. 2751-2759, Sept. 1994.
4. J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for high performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, Apr. 1995.
5. C. L. Huang and N. D. Arora, "Measurements and modeling of MOSFET I-V characteristics with polysilicon depletion effect," IEEE Trans. Electron Devices, vol. 40, pp. 2330-2337, Dec. 1993.
6. W. B. Wilson, U. K. Moon, and K. R. Lakshmikumar et al., "A CMOS self-calibrating frequency synthesizer," IEEE J. Solid-State Circuits, vol. 35, pp 1437-1444, Oct. 2000.
7. B. Miller and R. J. Conley, "A multiple modulator fractional divider," IEEE Trans. Instrum. Meas., vol. 40, pp. 578-583, June 1991.
8. C.-M. Hung, B. A. Floyd, N. Park, and K. K. O, "Fully integrated 5.35-GHz CMOS VCO's and prescalers," IEEE Trans. Microwave Theory Tech., vol. 49, pp. 17-22, Jan. 2001.
9. M. Danesh, J. R. Long, R. A. Hadaway, and D. L. Harame, "A Q-factor enhancement technique for MMIC inductors," in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, June 1998, pp. 183-186.
10. C.-M. Hung, Y.-C. Ho, I.-C. Wu, and K. K. O, "High-Q capacitors implemented in a CMOS process for low-power wireless applications," IEEE Trans. Microwave Theory Tech., pt. 1, vol. 46, pp. 505-511, May 1998.
11. J. B. Shyu, G. C. Temes, and F. Krummenacher, "Random error effects in matched MOS capacitors and current sources," IEEE J. Solid-State Circuits, vol. SC-19, pp. 948-955, Dec. 1984.
12. S. H. Lee and B. S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 27, pp. 1679-1688, Dec. 1992.
13. A. Kajiwara, and M. Nakagawa, "A new PLL frequency synthesizer with high switching speed," IEEE Trans. Veh. Technol., vol. 41, pp. 407-413, Nov. 1992.