A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 112-113

  Lee, Minjae ^a   Heidari, Mohammad E ^a   Abidi, Asad A ^a  

^a Department of Civil and Environmental Engineering   (United States)

Author keywords

Digital phase locked loop (PLL); Residue amplification; Wide bandwidth and time to digital converter (TDC)

Indexed keywords

BANDWIDTH; PHASE LOCKED LOOPS; PHASE NOISE; SIGNAL PROCESSING; VLSI CIRCUITS;

DIGITAL PHASE LOCKED LOOPS; HIGH RESOLUTION; IN-BAND PHASE NOISE; LOOP BANDWIDTH; RESIDUE AMPLIFICATION; SUBPICOSECOND; TIME TO DIGITAL CONVERTERS; WIDE BANDWIDTH AND TIME-TO-DIGITAL CONVERTERS;

FREQUENCY CONVERTERS;

EID: 51949095217     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585972     Document Type: Conference Paper

References (4)

1. R. B. Staszewski, J. Wallberg, S. Rezeq, et al, "All-Digital PLL and GSM/EDGE Transmitter in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 316-317, Feb., 2005.
2. M. H. Perrott, T.L. Tewksbury III, and C. G. Sodini,"A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, pp.2048-2059, Dec. 1997.
3. M. Lee and A. A. Abidi, "A 9b 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue," Symp. on VLSI Circuits, June. 2007, pp. 168-169.
4. R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P.T. Balsara, "1.3V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Transactions on Circuits and Systems II, vol.39, pp.220-224, Nov. 2004.