Thin-film devices for low power applications

Solid-State Electronics

Volumn 54, Issue 2, 2010, Pages 90-96

  Monfray, S ^a   Fenouillet Beranger, C ^b   Bidal, G ^a   Boeuf, F ^a   Denorme, S ^a   Huguenin, J L ^a   Samson, M P ^a   Loubet, N ^a   Hartmann, J M ^b   Campidelli, Y ^a   Destefanis, V ^a   Arvet, C ^a   Benotmane, K ^b   Clement, L ^a   Faynot, O ^b   Skotnicki, T ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

Bulk+; FDSOI; Localized SOI; Low power; SON; Ultra Thin Body devices

Indexed keywords

32-NM NODE; LOW POWER; LOW POWER APPLICATION; POWER CONSUMPTION; ROADMAP; THIN-FILM TECHNOLOGY; ULTRATHIN BODY;

NANOTECHNOLOGY; TECHNOLOGICAL FORECASTING;

THIN FILM DEVICES;

EID: 76349121303     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2009.12.013     Document Type: Article

References (23)

1. Fenouillet-Beranger C et al. Requirements for ultra-thin-film devices and new materials on CMOS roadmap. In: IEEE SOI conference; 2003.
2. Skotnicki T., et al. Innovative materials, devices and circuits for low power mobile multimedia. IEEE TED (2008) 96-130
3. Boeuf F et al. Impact of layout, interconnects and variability on CMOS technology roadmap. In: VLSI tech. dig.; 2007. p. 24-5.
4. MASTAR .
5. 2 6T-SRAM bitcell. In: IEDM tech. dig.; 2007. p. 267-70.
6. Fenouillet-Beranger C et al. FDSOI devices with thin BOX and ground plane integration for 32 nm node and below. In: Proceedings of ESSDERC; 2008. p. 206-9.
7. Fenouillet-Beranger C et al. Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below In: ESSDERC conference proceedings; 2009, p. 89-92.
8. Jurczak M., et al. Silicon-on-nothing (SON) - an innovative process for advanced CMOS. IEEE-TED 47 (2000) 2179
9. Monfray S et al. First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance. In: IEDM tech. dig.; 2001. p. 645-8.
10. Dutartre D et al. Si/SiGe ezpitaxy: a ubiquitous process for advanced electronics. In: Tech. dig. international electron devices meeting; 2007. p. 689-92.
11. Hartmann J.M., et al. Selective epitaxial growth of Si and SiGe for metal oxide semiconductor transistors. J Cryst Growth 259 4 (2003) 419-427
12. Hartmann J.M., et al. Reduced pressure-chemical vapour deposition of Si/SiGe heterostructures for nanoelectronics. Mater Sci Eng B 154-155 5 (2008) 76-84
13. Dutartre et al. Facet propagation in Si(Ge) epitaxy or etching. In: Proc. of ECS Cancun; 2006.
14. Loubet N., et al. High-density plane deposition kinetics and facet propagation in selective epitaxial growth. Semiconduct Sci Technol 22 (2007) 149-152
15. Borel S., et al. Control of the selectivity between SiGe and Si in isotropic etching processes. Jpn JAP 43 6B (2004) 3964-3966
16. Borel S., et al. Isotropic etching of SiGe alloys with high selectivity to similar materials. Microelectron Eng 73-74 (2004) 301
17. Loubet N et al. Selective etching of Si1-xGex versus Si with gaseous HCl for the formation of advanced CMOS devices. In: Proceedings of 5th int. conf. on silicon epitaxy and heterostructures; 2007. p. 83-4.
18. Loubet N et al. Si1-xGex/Si selective etch with HCl for thin Si-channel transistors integration. In: Proc. of int. conf. on solid state devices and material; 2007. p. 83-4.
19. Monfray S et al. Localized SOI technology: an innovative low cost self-aligned process for ultra thin si-film on thin BOX integration for low power applications. In: IEDM tech. dig.; 2007. p. 693-6.
20. th fluctuation technology in silicon on thin BOX featuring dual back-gate bias architecture, 007. In: IEDM tech. dig.; 2007. p. 475-8.
21. Ishigaki T et al. Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster. In: ESSDERC conference proceedings; 2008. p.198-201.
22. Bidal G et al. Planar bulk+ technology using TiN/Hf-based gate stack for low power applications. In: VLSI tech. dig.; 2008. p. 146-7.
23. Bidal G et al. Folded fully depleted bulk+ technology as a highly W-scaled planar solution. In: Proceedings of ESSDERC; 2008. p. 210-3.