Impact of a 10nm Ultra-Thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below

ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 88-91

  Fenouillet Beranger, C ^a,b   Perreau, P ^a,b   Denorme, S ^b   Tosti, L ^a   Andrieu, F ^a   Weber, O ^a   Barnola, S ^a   Arvet, C ^b   Campidelli, Y ^b   Haendler, S ^a   Beneyton, R ^b   Perrot, C ^b   De Buttet, C ^a,b   Gros, P ^b   Pham Nguyen, L ^b,c   Leverd, F ^b   Gouraud, P ^b   Abbate, F ^b   Baron, F ^b   Torres, A ^a   Laviron, C ^a   Pinzelli, L ^b   Vetier, J ^b   Borowiak, C ^b   Margain, A ^b   Delprat, D ^d   Boedt, F ^d   Bourdelle, K ^d   Nguyen, B Y ^d   Faynot, O ^a   Skotnicki, T ^b   more..

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c IMEP LAHC   (France)

^d PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

32-NM NODE; FULLY DEPLETED; GATE LENGTH; GATE TECHNOLOGY; GROUND PLANES; PERFORMANCE COMPARISON; PMOS DEVICES; SRAM CELL; ULTRA-THIN;

MOS DEVICES;

EID: 72849106645     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5325994     Document Type: Conference Paper

References (5)

1. C. Fenouillet-Beranger et al, IEDM'07, pp.267-270,
2. O. Weber et al, IEDM'08, pp.245-248;
3. N. Sugii et al, IEDM'08, pp.249-252
4. C. Fenouillet-Beranger et al, ESSDERC'08, pp.206-209;
5. J-P. Noel et al, Submitted to ESSDERC 2009