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Volumn , Issue , 2008, Pages 198-201

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

Author keywords

[No Author keywords available]

Indexed keywords

CMOSFETS; DRAIN LEAKAGES; INVERTER DELAYS; OFFSET SPACERS; OVERLAP LENGTHS; STANDBY POWERS;

EID: 58049133312     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2008.4681732     Document Type: Conference Paper
Times cited : (10)

References (11)
  • 1
    • 84924972584 scopus 로고    scopus 로고
    • T.C.Chen, Where CMOS is going: trendy hype vs. real technology, Solid-State Circuits, 2006 IEEE International Conference Digest of Technical Papers (ISSCC2006), pp. 1-18, February 2006.
    • T.C.Chen, "Where CMOS is going: trendy hype vs. real technology," Solid-State Circuits, 2006 IEEE International Conference Digest of Technical Papers (ISSCC2006), pp. 1-18, February 2006.
  • 5
    • 21644447069 scopus 로고    scopus 로고
    • Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control
    • December
    • R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, "Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control," IEDM Tech. Dig., pp. 631-634, December 2004.
    • (2004) IEDM Tech. Dig , pp. 631-634
    • Tsuchiya, R.1    Horiuchi, M.2    Kimura, S.3    Yamaoka, M.4    Kawahara, T.5    Maegawa, S.6    Ipposhi, T.7    Ohji, Y.8    Matsuoka, H.9
  • 10
    • 33745151094 scopus 로고    scopus 로고
    • H.-Y. Chen, C.-Y. Chang, C.-C. Huang, T.-X. Chung, S.-D. Liu, J.-R. Hwang, Y.-H. Liu, Y.-J. Chou, H.-J. Wu, K.-C. Shu, C.-K. Huang, J.-W. You, J.-J. Shin, C.-K. Chen, C.-H. Lin, J.-W. Hsu, B.-C. Perng, R-Y. Tsai, C.-C. Chen, J.-H. Shieh, H.-J. Tao, S.-C. Chen, T.-S. Gau, and F.-L. Yang, Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183um2 6T-SRAM Cell by Immersion Lithography, Tech. Dig. 2005 VLSI Technol., pp. 16-17, June 2005.
    • H.-Y. Chen, C.-Y. Chang, C.-C. Huang, T.-X. Chung, S.-D. Liu, J.-R. Hwang, Y.-H. Liu, Y.-J. Chou, H.-J. Wu, K.-C. Shu, C.-K. Huang, J.-W. You, J.-J. Shin, C.-K. Chen, C.-H. Lin, J.-W. Hsu, B.-C. Perng, R-Y. Tsai, C.-C. Chen, J.-H. Shieh, H.-J. Tao, S.-C. Chen, T.-S. Gau, and F.-L. Yang, "Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183um2 6T-SRAM Cell by Immersion Lithography," Tech. Dig. 2005 VLSI Technol., pp. 16-17, June 2005.
  • 11
    • 50249099761 scopus 로고    scopus 로고
    • S. Monfray, M. P. Samson, D. Dutartre, T. Ernst, E. Rouchouze, D. Renaud, B. Guillaumot, D. Chanemougame, G. Rabille, S. Borel, J. P. Colonna, C. Arvet, N. Loubet, Y. Campidelli, J. M. Hartmann, L. Vandroux, D. Bensahel, A. Toffoli, F. Allain, A. Margin, L. Clement, A. Quiroga, S. Deleonibus, and T. Skotnicki, Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications, IEDM Tech. Dig., pp. 693 - 696, December 2007.
    • S. Monfray, M. P. Samson, D. Dutartre, T. Ernst, E. Rouchouze, D. Renaud, B. Guillaumot, D. Chanemougame, G. Rabille, S. Borel, J. P. Colonna, C. Arvet, N. Loubet, Y. Campidelli, J. M. Hartmann, L. Vandroux, D. Bensahel, A. Toffoli, F. Allain, A. Margin, L. Clement, A. Quiroga, S. Deleonibus, and T. Skotnicki, "Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications," IEDM Tech. Dig., pp. 693 - 696, December 2007.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.