Impact of layout, interconnects and variability on CMOS technology roadmap

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 24-25

  Boeuf, Frederic ^a   Sellier, Manuel ^a   Farcy, Alexis ^a   Skotnicki, Thomas ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

INDUSTRIAL MANAGEMENT; POWER GENERATION;

6T SRAM; CIRCUIT PERFORMANCES; CMOS LOGIC; CMOS TECHNOLOGIES; LOADED RING; NEW GENERATION; POWER DISSIPATIONS; ROAD MAPS; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 44949208071     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339712     Document Type: Conference Paper

References (8)

1. ITRS Roadmap 2005 edition.; [2] T. Skotnicki et al., EDL vol 9, No3,1998;
2. S.D. Kim et al., TED vol. 49, 457472 , March 2002;
3. 2 Advanced Gate Materials 2006, pp 182-183,
4. F. Bœuf et al., SSDM 2006 pp 1046-1047;
5. MASTAR for ITRS, www.itrs.net/models.html
6. M. Sellier et al., sumitted to VLSI Symposium Circuits 2007 [8] A. Bhavnagwarla et al., IEDM 2005, pp 675-678;
7. K. Bernstein et al., IBM J. Res. &Dev. Vol. 50 No. 4/5, July/Sept 2006l
8. T.Mizuno et al, VLSI Symposium 1993, P 41-42