Planar bulk+ technology using TiN/Hf-based gate stack for low power applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 146-147

  Bidal, G ^a,b   Boeuf, F ^a   Denorme, S ^a   Loubet, N ^a   Laviron, C ^c   Leverd, F ^a   Barnola, S ^c   Salvetat, T ^c   Cosnier, V ^a   Martin, F ^c   Grosjean, M ^a   Perreau, P ^c   Chanemougame, D ^a   Haendler, S ^a   Marin, M ^a   Rafik, M ^a,b   Fleury, D ^a,b   Leyris, C ^a   Clement, L ^a   Sellier, M ^a   Monfray, S ^a   Bougueon, J ^a   Samson, M P ^a   Chapon, J D ^a   Gouraud, P ^a   GGhibaudo, ^b   Skotnicki, T ^a   more..

^a STMICROELECTRONICS   (France)

^b IMEP LAHC   (France)

^c CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

METALS; NONMETALS; SILICON;

FULLY DEPLETED; HIGH-K DIELECTRICS; LOW COSTS; METAL GATES; SILICON CHANNELS; SILICON-ON-NOTHING; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 51949101903     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588596     Document Type: Conference Paper

References (6)

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5. S. Monfray et al., in Tech. Digest of IEDM 2004, p 635
6. N. Loubet et al., in Proceedings of SSDM2007,p 716