Localized SOI technology: An innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 693-696

  Monfray, S ^a,b   Samson, M P ^a   Dutartre, D ^a   Ernst, T ^b   Rouchouze, E ^a   Renaud, D ^b   Guillaumot, B ^a   Chanemougame, D ^a   Rabille, G ^a   Borel, S ^b   Colonna, J P ^b   Arvet, C ^a   Loubet, N ^a   Campidelli, Y ^a   Hartmann, J M ^a   Vandroux, L ^b   Bensahel, D ^a   Toffoli, A ^b   Allain, F ^b   Margin, A ^a   Clement, L ^c   Quiroga, A ^a   Deleonibus, S ^b   Skotnicki, T ^a   more..

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c NXP SEMICONDUCTORS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; ENERGY CONSERVATION; SILICON; TECHNOLOGY;

ACTIVE AREAS; BULK CMOS; FULLY-DEPLETED; GA TE LENGTHS; GATE STACKS; INNOVATIVE APPROACHES; LOW COSTS; LOW POWER APPLICATIONS; NMOS DEVICES; SELF ALIGNED PROCESSES; SI-FILMS; SOI TECHNOLOGY; SON TECHNOLOGY; SUCCESSFUL INTEGRATION;

SUBSTRATES;

EID: 50249099761     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4419040     Document Type: Conference Paper

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