-
1
-
-
37249021916
-
-
O. A. Amusan, L. W. Massengill, B. L. Bhuva, S. DasGupta, A. F. Witulski, and J. R. Ahlbin. Design techniques to reduce set pulse widths in deep-submicron combinational logic. IEEE Tran. Nuclear Science, 54(6):2060-2064, Dec 2007.
-
O. A. Amusan, L. W. Massengill, B. L. Bhuva, S. DasGupta, A. F. Witulski, and J. R. Ahlbin. Design techniques to reduce set pulse widths in deep-submicron combinational logic. IEEE Tran. Nuclear Science, 54(6):2060-2064, Dec 2007.
-
-
-
-
2
-
-
12344287173
-
-
W. Bartlett and L. Spainhower. Commercial fault tolerance: a tale of two systems. IEEE Tran. Dependable and Secure Computing, 1(1):87-96, Jan-Mar 2004.
-
W. Bartlett and L. Spainhower. Commercial fault tolerance: a tale of two systems. IEEE Tran. Dependable and Secure Computing, 1(1):87-96, Jan-Mar 2004.
-
-
-
-
4
-
-
0041633858
-
Parameter variations and impact on circuits and microarchitecture
-
Jul
-
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. Parameter variations and impact on circuits and microarchitecture. In Proc. Design Automation Conf., pages 338-342, Jul 2003.
-
(2003)
Proc. Design Automation Conf
, pp. 338-342
-
-
Borkar, S.1
Karnik, T.2
Narendra, S.3
Tschanz, J.4
Keshavarzi, A.5
De, V.6
-
5
-
-
0036474722
-
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
-
Feb
-
K. Bowman, S. Duvall, and J. Meindl. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. IEEE Jour. Solid-State Circuits, 37(2):183-190, Feb 2002.
-
(2002)
IEEE Jour. Solid-State Circuits
, vol.37
, Issue.2
, pp. 183-190
-
-
Bowman, K.1
Duvall, S.2
Meindl, J.3
-
6
-
-
0027848063
-
A logic-level model for α particle hits in cmos circuits
-
Aug
-
H. Cha and J. H. Patel. A logic-level model for α particle hits in cmos circuits. In Proc. Int'l Conf. Circuit Design, pages 538-542, Aug 1993.
-
(1993)
Proc. Int'l Conf. Circuit Design
, pp. 538-542
-
-
Cha, H.1
Patel, J.H.2
-
8
-
-
0038721289
-
-
P. E. Dodd and L. W. .Massengill. Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Tran. Nuclear Science, 50(3):583-602, Jun 2003.
-
P. E. Dodd and L. W. .Massengill. Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Tran. Nuclear Science, 50(3):583-602, Jun 2003.
-
-
-
-
9
-
-
51549113427
-
A fast, analytical estimator for the seu-induced pulse width in combinational designs
-
Jul
-
R. Garg, C. Nagpal, and S. P. Khatri. A fast, analytical estimator for the seu-induced pulse width in combinational designs. In Proc. Design Automation Conf., pages 918-923, Jul 2008.
-
(2008)
Proc. Design Automation Conf
, pp. 918-923
-
-
Garg, R.1
Nagpal, C.2
Khatri, S.P.3
-
11
-
-
33847715275
-
Mars-c: Modeling and reduction of soft errors in combinational circuits
-
Jul
-
N. Miskov-Zivanov and D. Marculescu. Mars-c: modeling and reduction of soft errors in combinational circuits. In Proc. Design Automation Conf., pages 767-772, Jul 2006.
-
(2006)
Proc. Design Automation Conf
, pp. 767-772
-
-
Miskov-Zivanov, N.1
Marculescu, D.2
-
13
-
-
15044363155
-
-
S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim. Robust system design with built-in soft error resilience. IEEE Tran. Computer, 38(2):43-52, Feb 2005.
-
S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim. Robust system design with built-in soft error resilience. IEEE Tran. Computer, 38(2):43-52, Feb 2005.
-
-
-
-
14
-
-
84886478721
-
Closed-form simulation and robustness models for seu-tolerant design
-
May
-
K. Mohanram. Closed-form simulation and robustness models for seu-tolerant design. In Proc. VLSI Test Symp., pages 327-333, May 2005.
-
(2005)
Proc. VLSI Test Symp
, pp. 327-333
-
-
Mohanram, K.1
-
16
-
-
70350363207
-
-
Nangate Inc, Available at
-
Nangate Inc. Nangate 45nm Open Library, 2008. Available at http://www.nangate.com/.
-
(2008)
Nangate 45nm Open Library
-
-
-
17
-
-
4243681615
-
-
Nanoscale Integration and Modeling Group, Available at
-
Nanoscale Integration and Modeling Group. Predictive Technology Model, 2008. Available at http://www.eas.asu.edu/ptm/.
-
(2008)
Predictive Technology Model
-
-
-
19
-
-
84944062057
-
A model for transient fault propagation in combinational logic
-
M. Omana, G. Papasso, D. Rossi, and C. Metra. A model for transient fault propagation in combinational logic. In Proc. Int'l On-Line Testing Symp., pages 111-115, 2003.
-
(2003)
Proc. Int'l On-Line Testing Symp
, pp. 111-115
-
-
Omana, M.1
Papasso, G.2
Rossi, D.3
Metra, C.4
-
20
-
-
33748538027
-
Seat-la: A soft error analysis tool for combinational logic
-
Jan
-
R. Rajaraman, J. S. Kim, N. Vijaykrishnan, Y. Xie, and M. J. Irwin. Seat-la: a soft error analysis tool for combinational logic. In Proc. Int'l Conf. VLSI Design, pages 499-502, Jan 2006.
-
(2006)
Proc. Int'l Conf. VLSI Design
, pp. 499-502
-
-
Rajaraman, R.1
Kim, J.S.2
Vijaykrishnan, N.3
Xie, Y.4
Irwin, M.J.5
-
21
-
-
34548120787
-
Variation impact on ser of combinational circuits
-
K. Ramakrishnan, R. Rajaraman, S. Suresh, N. Vijaykrishnan, Y. Xie, and M. J. Irwin. Variation impact on ser of combinational circuits. In Proc. Int'l Smyp. Quality Electronic Design, pages 911-916, 2007.
-
(2007)
Proc. Int'l Smyp. Quality Electronic Design
, pp. 911-916
-
-
Ramakrishnan, K.1
Rajaraman, R.2
Suresh, S.3
Vijaykrishnan, N.4
Xie, Y.5
Irwin, M.J.6
-
22
-
-
34047185427
-
An efficient static algorithm for computing the soft error rates of combinational circuits
-
March
-
R. Rao, K. Chopra, D. Blaauw, and D. Sylvester. An efficient static algorithm for computing the soft error rates of combinational circuits. In Proc. Design Automation and Test in Europe Conf., pages 164-169, March 2006.
-
(2006)
Proc. Design Automation and Test in Europe Conf
, pp. 164-169
-
-
Rao, R.1
Chopra, K.2
Blaauw, D.3
Sylvester, D.4
-
23
-
-
77955989630
-
-
Semiconductor Roadmap Committee of Japan, Available at
-
Semiconductor Roadmap Committee of Japan. Parameters of Low Power SoC Design, 2003. Available at http://strj-jeita.elisasp.net/pdf-nenjihoukoku- 0303-roadmap/3-13-etsukei-ask-force.pdf.
-
(2003)
Parameters of Low Power SoC Design
-
-
-
24
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proc. Int'l Conf. Dependable Systems and Networks, pages 389-398, 2002.
-
(2002)
Proc. Int'l Conf. Dependable Systems and Networks
, pp. 389-398
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
-
25
-
-
0003401675
-
A tutorial on support vector regression
-
Technical report, Statistics and Computing, 2003
-
A. J. Smola, B. Scholkopf, and B. S. Olkopf. A tutorial on support vector regression. Technical report, Statistics and Computing, 2003.
-
-
-
Smola, A.J.1
Scholkopf, B.2
Olkopf, B.S.3
-
26
-
-
0033335620
-
-
Y. Tosaka, H. Hanata, T. Itakura, and S. Satoh. Simulation technologies for cosmic ray neutron-induced soft errors: models and simulation systems. IEEE Tran. Nuclear Science, 46(3):774-780, Jun 1999.
-
Y. Tosaka, H. Hanata, T. Itakura, and S. Satoh. Simulation technologies for cosmic ray neutron-induced soft errors: models and simulation systems. IEEE Tran. Nuclear Science, 46(3):774-780, Jun 1999.
-
-
-
-
27
-
-
0003450542
-
-
Springer-Verlag New York, Inc, New York, NY, USA
-
V. N. Vapnik. The nature of statistical learning theory. Springer-Verlag New York, Inc., New York, NY, USA, 1995.
-
(1995)
The nature of statistical learning theory
-
-
Vapnik, V.N.1
-
30
-
-
46749103715
-
Design for resilience to soft errors and variations
-
Jul
-
M. Zhang, T. Mak, J. Tschanz, K. Kim, N. Seifert, and D. Lu. Design for resilience to soft errors and variations. In Proc. Int'l On-Line Test Symp., pages 23-28, Jul 2007.
-
(2007)
Proc. Int'l On-Line Test Symp
, pp. 23-28
-
-
Zhang, M.1
Mak, T.2
Tschanz, J.3
Kim, K.4
Seifert, N.5
Lu, D.6
|