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Volumn , Issue , 2007, Pages 911-916

Variation impact on ser of combinational circuits

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER TRANSMISSION; ERROR ANALYSIS; PARAMETER ESTIMATION;

EID: 34548120787     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2007.168     Document Type: Conference Paper
Times cited : (44)

References (16)
  • 1
    • 34548137076 scopus 로고    scopus 로고
    • ITRS-2003, Critical reliability challenges for the International Technology Roadmap for Semiconductors, International Sematech Technology transfer 03024377A-TR, 2003.
    • ITRS-2003, Critical reliability challenges for the International Technology Roadmap for Semiconductors, International Sematech Technology transfer 03024377A-TR, 2003.
  • 3
    • 0036474722 scopus 로고    scopus 로고
    • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
    • Feb, Pages
    • K. A. Bowman,S. G. Duvall, J. D. Meindl, Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, Volume 37, Issue 2, Feb. 2002 Page(s):183-190.
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , Issue.2 , pp. 183-190
    • Bowman, K.A.1    Duvall, S.G.2    Meindl, J.D.3
  • 7
    • 25144518593 scopus 로고    scopus 로고
    • Process variation in embedded memories: Failure analysis and variation aware architecture
    • September
    • A. Agarwal, B. C. Paul, S. Mukhopadhyay and K. Roy, Process variation in embedded memories: failure analysis and variation aware architecture, IEEE Journal of Solid-state Circuits, Vol.40, pp. 1804-1814, September 2005.
    • (2005) IEEE Journal of Solid-state Circuits , vol.40 , pp. 1804-1814
    • Agarwal, A.1    Paul, B.C.2    Mukhopadhyay, S.3    Roy, K.4
  • 9
    • 0031102965 scopus 로고    scopus 로고
    • The threshold-voltage model of MOSFET devices with localized interface charge
    • Y. S. Jean and C. Y. Wu, The threshold-voltage model of MOSFET devices with localized interface charge, IEEE Transactions on Electron Devices, 1997.
    • (1997) IEEE Transactions on Electron Devices
    • Jean, Y.S.1    Wu, C.Y.2
  • 11
    • 0030704451 scopus 로고    scopus 로고
    • H. H. Chen and D.D .Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, Proceedings of Design Automation Conference, 1997.
    • H. H. Chen and D.D .Ling, Power supply noise analysis methodology for deep-submicron VLSI chip design, Proceedings of Design Automation Conference, 1997.
  • 16
    • 34548132151 scopus 로고    scopus 로고
    • http://www.eas.asu.edu/~ptm/reliability/PTM_NBTI_Beta.pdf.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.