On the role of timing masking in reliable logic circuit design

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 924-929

  Krishnaswamy, Smita ^a   Markov, Igor L ^a,b   Hayes, John P ^a  

^a University of Michigan   (United States)

^b Synplicity Inc   (United States)

Author keywords

SEUs; Soft errors; Timing

Indexed keywords

LATCHING WINDOW; SEUS; SOFT ERRORS; TIMING;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ERROR CORRECTION; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; MICROPROCESSOR CHIPS; STATIC ANALYSIS; SWITCHING CIRCUITS; SWITCHING THEORY; TIME MEASUREMENT; TIMING CIRCUITS; WINDOWS;

ERROR ANALYSIS;

EID: 51549088435     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555952     Document Type: Conference Paper

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