Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 61-64

  Barral, V ^a,b   Poiroux, T ^a   Andrieu, F ^a   Buj Dufournet, C ^a   Faynot, O ^a   Ernst, T ^a   Brevard, L ^a   Fenouillet Beranger, C ^a   Lafond, D ^a   Hartmann, J M ^a   Vidal, V ^a   Allain, F ^a   Daval, N ^c   Cayrefourcq, I ^c   Tosti, L ^a   Munteanu, D ^b   Autran, J L ^b   Deleonibus, S ^a  

^a CEA LETI   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

^c PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; HAFNIUM OXIDES; LOGIC GATES; SCALABILITY; TIN;

BURIED OXIDES; CMOS TECHNOLOGY; ELECTROSTATIC CONTROL; FRINGING FIELDS; IN-DEPTH ANALYSIS; OFF-STATE CURRENT; STRAIN INDUCED; SUBTHRESHOLD SWING;

FILM THICKNESS;

EID: 44949085361     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418863     Document Type: Conference Paper

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