Ultra low-power CMOS IC using partially-depleted SOI technology

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 57-60

  Ebina, Akihiko ^a   Kadowaki, Tadao ^a   Sato, Yoko ^a   Yamaguchi, Masayuki ^a  

^a SEIKO EPSON CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; TIMING CIRCUITS;

JUNCTION CAPACITANCE; JUNCTION LEAKAGE; LOW POWER CIRCUIT TECHNOLOGY; WRIST WATCH;

CMOS INTEGRATED CIRCUITS;

EID: 0033698751     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)