The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

Solid-State Electronics

Volumn 47, Issue 6, 2003, Pages 1111-1115

  Li, Ying ^a   Niu, Guofu ^a   Cressler, John D ^b   Patel, Jagdish ^c   Liu, S T ^d   Reed, Robert A ^e   Mojarradi, Mohammad M ^c   Blalock, Benjamin J ^f  

^a AUBURN UNIVERSITY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^d HONEYWELL TECHNOLOGY CENTER   (United States)

^e NASA HEADQUARTERS   (United States)

^f UNIVERSITY OF TENNESSEE   (United States)

Author keywords

CMOS; High temperature electronics; Impact ionization; Low temperature electronics; Partially depleted; Radiation; SOI

Indexed keywords

CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; CRYOGENICS; FIELD EFFECT TRANSISTORS; IMPACT IONIZATION; IONIZING RADIATION; PARAMETER ESTIMATION; THRESHOLD VOLTAGE;

HIGH TEMPERATURE ELECTRONICS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0037409039     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00516-6     Document Type: Article

References (10)

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