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Volumn , Issue , 2009, Pages 439-444

Trend from ICs to 3D ICs to 3D systems

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; 3D SYSTEMS; ALTERNATIVE PATH; ENTIRE SYSTEM; FINE PITCH; IC INDUSTRY; MINIATURIZATION TECHNOLOGIES; MOORE'S LAW; NANO SCALE; SYSTEM INTERCONNECTIONS; THERMAL MATERIALS; TOTAL BENEFITS; TRANSISTOR CHIPS; WAFER LEVEL;

EID: 74249100442     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280817     Document Type: Conference Paper
Times cited : (48)

References (34)
  • 1
    • 0028378852 scopus 로고
    • Multilevel Thin Film Packaging: Applications and Processes for High Performance Systems, IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B
    • Feb
    • Eric Perfecto and Keshav Prasad, "Multilevel Thin Film Packaging: Applications and Processes for High Performance Systems," IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B: Advanced Packaging, Vol. 17 No.1, pp. 38-49, Feb 1994.
    • (1994) Advanced Packaging , vol.17 , Issue.1 , pp. 38-49
    • Perfecto, E.1    Prasad, K.2
  • 2
    • 0025512935 scopus 로고
    • Interconnection processes and materials
    • Greg E. Blonder, R. A. Gottscho, and King L. Tai, "Interconnection processes and materials," AT&T Tech. J., vol. 69, pp. 46, 1990.
    • (1990) AT&T Tech. J , vol.69 , pp. 46
    • Blonder, G.E.1    Gottscho, R.A.2    Tai, K.L.3
  • 4
  • 5
    • 0042729971 scopus 로고    scopus 로고
    • Multilayer thin-film technology enabling technology for solving high-density interconnect and assembly problems
    • Eric Beyne et al, "Multilayer thin-film technology enabling technology for solving high-density interconnect and assembly problems", Nuclear Instruments and Methods in Physics Research A, 509 (2003) pp. 191-199.
    • (2003) Nuclear Instruments and Methods in Physics Research A , vol.509 , pp. 191-199
    • Beyne, E.1
  • 6
    • 74249120705 scopus 로고    scopus 로고
    • 3D TSV Interconnects Devices & Systems - 2008 Report
    • Yole Development
    • "3D TSV Interconnects Devices & Systems - 2008 Report", Yole Development, www.yole.fr
  • 7
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration
    • May
    • K. Banerjee, et al., "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration, Proceeding of the IEEE, Vol. 89, No. 5, pp. 602-633, May, 2001
    • (2001) Proceeding of the IEEE , vol.89 , Issue.5 , pp. 602-633
    • Banerjee, K.1
  • 8
    • 18144413062 scopus 로고    scopus 로고
    • P. Garrou, Future ICs go Vertical, Semiconductor Packaging, pp. SP.10-SP.16, February, 2005.
    • P. Garrou, "Future ICs go Vertical," Semiconductor Packaging, pp. SP.10-SP.16, February, 2005.
  • 10
    • 34748923685 scopus 로고    scopus 로고
    • Three dimensional chip stacking using a wafer-to-wafer integration
    • IEEE, June
    • R. Chatterjee, et al., "Three dimensional chip stacking using a wafer-to-wafer integration," Proc. International Interconnect Technology Conference, IEEE, June, 2007, pp. 81-83.
    • (2007) Proc. International Interconnect Technology Conference , pp. 81-83
    • Chatterjee, R.1
  • 11
    • 33646236322 scopus 로고    scopus 로고
    • Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology
    • P. R. Morrow, C.-M. Park, S. Ramanathan, M. J. Kobrinsky, and M. Harmes, "Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology", IEEE Electron Dev. Lett., Vol. 27, No. 5, (2006), pp. 335-337.
    • (2006) IEEE Electron Dev. Lett , vol.27 , Issue.5 , pp. 335-337
    • Morrow, P.R.1    Park, C.-M.2    Ramanathan, S.3    Kobrinsky, M.J.4    Harmes, M.5
  • 12
    • 33947407658 scopus 로고    scopus 로고
    • Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs
    • June
    • R. Patti, "Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs," Proceedings of the IEEE, Vol. 94, No. 6, pp. 1214-1224, June 2006.
    • (2006) Proceedings of the IEEE , vol.94 , Issue.6 , pp. 1214-1224
    • Patti, R.1
  • 13
    • 74249090272 scopus 로고    scopus 로고
    • R. E. Jones, et al., Technology and Application of 3D Technology, International Conference on Integrated Circuit Design and Technology, Austin, TX, May 30-June 1, 2007, published in the Proceedings of the International Conference on Integrated Circuit Design and Technology 2007, IEEE Electron Device Society, Piscataway, NJ (2007).
    • R. E. Jones, et al., "Technology and Application of 3D Technology," International Conference on Integrated Circuit Design and Technology, Austin, TX, May 30-June 1, 2007, published in the Proceedings of the International Conference on Integrated Circuit Design and Technology 2007, IEEE Electron Device Society, Piscataway, NJ (2007).
  • 14
    • 25844453501 scopus 로고    scopus 로고
    • Development of Next-Generation System-on-Package (SOP) Technology Based on Silicon Carriers with Fine-pitch Chip Interconnection
    • July/September
    • J. U. Knickerbocker, et al., "Development of Next-Generation System-on-Package (SOP) Technology Based on Silicon Carriers with Fine-pitch Chip Interconnection," IBM J. Res. & Dev., Vol 49, No. 4/5, July/September, 2005, pp. 725-753.
    • (2005) IBM J. Res. & Dev , vol.49 , Issue.4-5 , pp. 725-753
    • Knickerbocker, J.U.1
  • 18
    • 35348874767 scopus 로고    scopus 로고
    • A. den Dekker, A. van Geelen, P. van der Wel, R. Koster1, E.C. Rodenburg, Passi4: The next Technology for Passive Integration on Silicon, Proceedings - Electronic Components and Technology Conference, ECTC 2007, pp. 968-973.
    • A. den Dekker, A. van Geelen, P. van der Wel, R. Koster1, E.C. Rodenburg, Passi4: The next Technology for Passive Integration on Silicon, Proceedings - Electronic Components and Technology Conference, ECTC 2007, pp. 968-973.
  • 22
    • 33947526753 scopus 로고    scopus 로고
    • Low temperature carbon nanotube film transfer via conductive polymer composites
    • 12, Art 125203
    • H. Jiang, L. Zhu, K. Moon, C. P. Wong, "Low temperature carbon nanotube film transfer via conductive polymer composites", Nanotechnology Vol. 18 (12), Art. No. 125203 (2007).
    • (2007) Nanotechnology , vol.18
    • Jiang, H.1    Zhu, L.2    Moon, K.3    Wong, C.P.4
  • 23
    • 33751217472 scopus 로고    scopus 로고
    • Microcontacts with sub-30 lm pitch for 3D chip-on-chip integration
    • H. Huebner et al, "Microcontacts with sub-30 lm pitch for 3D chip-on-chip integration," Microelectronic Engineering, Vol 83, 2006, pp 2155-2162
    • (2006) Microelectronic Engineering , vol.83 , pp. 2155-2162
    • Huebner, H.1
  • 27
    • 0037481243 scopus 로고    scopus 로고
    • An advanced multichip module (MCM) for high-performance UNIX servers
    • November
    • J. U. Knickerbocker et al, "An advanced multichip module (MCM) for high-performance UNIX servers," IBM Journal of Research & Development, Vol. 46, No. 6, November 2002, pp 779-804
    • (2002) IBM Journal of Research & Development , vol.46 , Issue.6 , pp. 779-804
    • Knickerbocker, J.U.1
  • 32
    • 74249097603 scopus 로고    scopus 로고
    • Compliant microelectronic mounting device,
    • US Patent number: 5706174
    • T. H. Distefano et al, "Compliant microelectronic mounting device," US Patent number: 5706174, 1998
    • (1998)
    • Distefano, T.H.1
  • 33
    • 74249109824 scopus 로고    scopus 로고
    • Compliant off-chip interconnects,
    • US Patent number: 6784378
    • Qi Zhu et al, "Compliant off-chip interconnects," US Patent number: 6784378, 2004
    • (2004)
    • Zhu, Q.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.