Bed of Nails - 100 microns pitch wafer level interconnections process

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004

Volumn , Issue , 2004, Pages 444-449

  Rao, Vempati Srinivasa ^a,b   Tay, A A O ^a   Kripesh, V ^b   Lim, C T ^a   Yoon, Seung Wook ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SOLDERING ALLOYS; THERMAL CYCLING;

CHIP-TO-SUBSTRATE INTERCONNECTION TECHNOLOGY; COPPER COLUMNS; TEMPERATURE CYCLING;

ELECTRONICS PACKAGING;

EID: 28444471655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. th VLSI packaging Workshop, Kyoto, 1998, pp. 114.
4. Hiroshi Yamada et. al, "Adavanced Copper Column Based Solder Bump for Flip Chip Interconnection," The International Journal of Microcircuits and Electronic Packaging, Vol. 21, No. 1, 1998, pp. 15.
5. International Technology Roadmap for Semiconductors (2003)- Assembly and Packaging. [Online]. Available: http//piblic.itrs.net
6. C. S. Chang et. al, "Future challenges in electronics packaging," Circuits Devices, 1998, pp.45-54.
7. Lunyu Ma et. al, "Compliant cantilevered sping interconnects for flip-chip packaging," proceedings of 2001 Electronic Components and Technology Conference.
8. M. Bakir et. al, " Sea of Leads ultra-high density compliant wafer level packaging technology," Proceedings of 2002 Electronic Components and Technology Conference, pp. 1087-1094.
9. JSR resist material process data sheet. Available: www.jsr.co.jp