50 micron pitch wafer level packaging testbed with reworkable IC-package nano interconnects

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2005, Pages 1139-1146

  Aggarwal, Ankur O ^a   Raj, P Markondeya ^a   Sundaram, Venky ^a   Ravi, D ^a   Koh, Sauwee ^a   Mullapudi, Ravi ^b   Tummala, Rao R ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Hionix Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL PERFORMANCE; HIGH-DENSITY SUBSTRATES; INTERCONNECT DENSITY; MICRO-ELECTRONIC DEVICES;

COMPUTER SIMULATION; INTEGRATED CIRCUITS; MICROELECTRONICS; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; SILICON WAFERS; SOLDERING ALLOYS;

ELECTRONICS PACKAGING;

EID: 24644437399     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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