A diagnosis algorithm for extreme space compaction

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1355-1360

  Holst, Stefan ^a   Wunderlich, Hans Joachim ^a  

^a UNIVERSITY OF STUTTGART   (Germany)

Author keywords

Compaction; Design for test; Diagnosis; Embedded diagnosis; Multi site test

Indexed keywords

AUTOMATIC TESTING; COMPACTION; COST REDUCTION; DIAGNOSIS; EQUIPMENT TESTING; LEARNING ALGORITHMS;

AUTOMATIC TEST EQUIPMENT; DESIGN FOR TEST; DIAGNOSIS ALGORITHMS; DIAGNOSTIC RESOLUTION; MULTI-SITE TESTING; MULTI-SITE TESTS; TEST APPLICATION TIME; TEST-RESPONSE COMPACTION;

BUILT-IN SELF TEST;

EID: 70350047056     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090875     Document Type: Conference Paper

References (33)

1. F. Poehl, J. Rzeha, M. Beck, M. Gössel, R. Arnold, and P. Ossimitz, "On-chip evaluation, compensation, and storage of scan diagnosis data - a test time efficient scan diagnosis architecture," in 11th European Test Symposium (ETS 2006), 21-24 May 2006, Southhampton, UK. IEEE Computer Society, May 2006, pp. 239-246.
2. S. K. Goel and E. J. Marinissen, "On-chip test infrastructure design for optimal multi-site testing of system chips," in DATE. IEEE Computer Society, 2005, pp. 44-49.
3. E. Volkerink, A. Khoche, J. Rivoir, and K. Hilliges, "Test economics for multi-site test with modern cost reduction techniques," in Proceedings 20th IEEE VLSI Test Symposium, 2002. (VTS 2002)., 2002, pp. 411-416.
4. V. Iyengar, S. Goel, E. Marinissen, and K. Chakrabarty, "Test resource optimization for multi-site testing of socs under ate memory depth constraints." in Proceedings. International Test Conference, 7-10 Oct. 2002, 2002, pp. 1159-1168.
5. J. Rivoir, "Parallel test reduces cost of test more effectively than just a cheap tester," in Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International, 14-16 2004, pp. 263-272.
6. A. Kinsman, S. Ollivierre, and N. Nicolici, "Diagnosis of logic circuits using compressed deterministic data and on-chip response comparison," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, no. 5, pp. 537-548, May 2006.
7. J. Rajski, J. Tyszer, C. Wang, and S. M. Reddy, "Finite memory test response compactors for embedded test applications," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 24, no. 4, pp. 622-634, 2005.
8. A. Leininger, M. Gössel, and P. Muhmenthaler, "Diagnosis of scanchains by use of a configurable signature register and error-correcting codes," in 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, vol. 2. IEEE Computer Society, 2004, pp. 1302-1307.
9. N. Touba, "X-canceling misr an x-tolerant methodology for compacting output responses with unknowns using a misr," in Proceedings 2007 International Test Conference (ITC 2007), October 23-25, 2007, Santa Clara, CA, USA. IEEE, Oct. 2007, pp. 1-10.
10. A. Leininger, P. Muhmenthaler, W.-T. Cheng, N. Tamarapalli, W. Yang, and H. Tsai, "Compression mode diagnosis enables high volume monitoring diagnosis flow," in Proceedings IEEE International Test Conference 2005, November 810, 2005, Austin Convention Center Austin, Texas, USA. IEEE Computer Society, Nov. 2005, p. 7.3.
11. S. Mitra and K. S. Kim, "X-compact: an efficient response compaction technique," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 23, no. 3, pp. 421-432, March 2004.
12. H. P. E. Vranken, S. K. Goel, A. Glowatz, J. Schlöffel, and F. Hapke, "Fault detection and diagnosis with parity trees for space compaction of test responses," in Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, E. Sentovich, Ed. ACM, 2006, pp. 1095-1098.
13. B. Koenemann, "LFSR-coded test patterns for scan designs," in Proceedings of the European Test Conference, Munich, Germany, 1991, pp. 237-242.
14. S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers," IEEE Trans. Computers, vol. 44, no. 2, pp. 223-233, 1995.
15. J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, "Embedded deterministic test," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 23, no. 5, pp. 776-792, 2004.
16. I. Hamzaoglu and J. Patel, "Reducing test application time for full scan embedded cores." in Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, WI, USA, 15-18 June 1999, 1999, pp. 260-267.
17. L. Li, K. Chakrabarty, S. Kajihara, and S. Swaminathan, "Efficient space/time compression to reduce test data volume and testing time for ip cores," in VLSI Design, 2005. 18th International Conference on, Jan. 2005, pp. 53-58.
18. Y. Doi, S. Kajihara, X. Wen, L. Li, and K. Chakrabarty, "Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation," Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific, vol. 1, pp. 59-64, Jan. 2005.
19. M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu, "On-chip compression of output responses with unknown values using lfsr reseeding," in Proc. of IEEE International Test Conference, September 2003, pp. 1060-1068.
20. H. Tang, C. Wang, J. Rajski, S. Reddy, J. Tyszer, and I. Pomeranz, "On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios." in 18th International Conference on VLSI Design, 2005, pp. 59-64.
21. Y. Tang, H.-J. Wunderlich, H. P. E. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker, "X-masking during logic bist and its impact on defect coverage." in Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA. IEEE, 2004, pp. 442-451.
22. W.-T. Cheng, K.-H. Tsai, Y. Huang, N. Tamarapalli, and J. Rajski, "Compactor independent direct diagnosis," in 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan. IEEE Computer Society, Nov. 2004, pp. 204-209.
23. K. K. Saluja and M. Karpovsky, "Testing computer hard-ware through data compression in space and time." in Proceedings IEEE International Test Conference (ITC), 1983, 1983, p. 8389.
24. J. Patel, S. Lumetta, and S. Reddy, "Application of saluja-karpovsky compactors to test responses with many unknowns." in Proceedings on 21st VLSI Test Symposium, 27 April-1 May 2003, 2003, pp. 107-112.
25. S. Das, T. Barakat, E. Petriu, M. Assaf, and K. Chakrabarty, "Space compression revisited," Instrumentation and Measurement, IEEE Transactions on, vol. 49, no. 3, pp. 690-705, Jun 2000.
26. C.-W. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "Test and diagnosis of word-oriented multiport memories," in Proc. 21st IEEE VLSI Test Symposium, May 2003, p. 248.
27. C. Liu and K. Chakrabarty, "Failing vector identification based on overlapping intervals of test vectors in a scan-bist environment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 593-604, May 2003.
28. M. Elm and H.-J. Wunderlich, "Scan chain organization for embedded diagnosis," in Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008. IEEE, 2008, pp. 468-473.
29. R. Desineni, O. Poku, and R. D. Blanton, "A logic diagnosis methodology for improved localization and extraction of accurate defect behavior," in Proceedings IEEE International Test Conference 2006, Santa Clara, CA, USA, October 24-26, 2006. IEEE Computer Society, Oct. 2006, p. 12.3.
30. J. A. Waicukauski and E. Lindbloom, "Failure diagnosis of structured VLSI," IEEE Design & Test of Computers, vol. 6, no. 4, pp. 49-60, Aug 1989.
31. J. Rajski, J. Tyszer, G. Mrugalski, W.-T. Cheng, N. Mukherjee, and M. Kassab, "X-press compactor for 1000x reduction of test data," in Proceedings IEEE International Test Conference 2006, Santa Clara, CA, USA, October 24-26, 2006. IEEE Computer Society, Oct. 2006, pp. 1-10.
32. S. Holst and H.-J. Wunderlich, "Adaptive debug and diagnosis without fault dictionaries," in Proceedings European Test Symposium, May 20-24 2007, Freiburg, Germany. IEEE Computer Society, May 2007, pp. 7-12.
33. L. M. Huisman, "Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 23, no. 1, pp. 91-101, January 2004.