On-chip test infrastructure design for optimal multi-site testing of system chips

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 44-49

  Goel, Sandeep Kumar ^a   Marinissen, Erik Jan ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COSTS; OPTIMIZATION; SILICON WAFERS; THROUGHPUT;

ATE CHANNELS; MULTI-SITE TESTING; SYSTEM-ON-CHIP; WAFER TESTING;

MICROPROCESSOR CHIPS;

EID: 33646904810     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.231     Document Type: Conference Paper

References (14)

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