Parallel test reduces cost of test more effectively than just a cheap tester

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn 29, Issue , 2004, Pages 263-272

  Rivoir, Jochen ^a  

^a AGILENT TECHNOLOGIES   (Germany)

Author keywords

ATE; Cost of test; I O bandwidth matching; Low cost ATE; Multi site test; Probe card; Reduced pin count testing; Test economics

Indexed keywords

BANDWIDTH; CALIBRATION; COST BENEFIT ANALYSIS; COSTS; DESIGN FOR TESTABILITY; ELECTRIC DISTORTION; OPTIMIZATION; PARAMETER ESTIMATION; PROBLEM SOLVING; RELIABILITY; SENSITIVITY ANALYSIS;

ATE; COST OF TEST; I/O BANDWIDTH MATCHING; LOW-COST ATE; MULTI-SITE TEST; PROBE-CARD; REDUCED PIN-COUNT TESTING; TEST ECONOMICS;

TRANSISTORS;

EID: 4644305525     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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