Finite memory test response compactors for embedded test applications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 4, 2005, Pages 622-634

  Rajski, Janusz ^a   Tyszer, Jerzy ^b   Reddy, Sudhakar M ^c   Wang, Chen ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b POZNAN UNIVERSITY OF TECHNOLOGY   (Poland)

^c IA United States   (United States)

Author keywords

Convolutional compactors (CCS); Design for testability (DFT); Embedded test; Spatial compactors; Test response compaction; Time compactors; Unknown states

Indexed keywords

BENCHMARKING; COMPACTION; DIAGNOSIS; ERROR DETECTION; PRODUCT DESIGN; ROUTERS; STATE ASSIGNMENT; TOOLS;

CONVOLUTIONAL COMPACTORS (CCS); DESIGN FOR TESTABILITY (DFT); EMBEDDED TEST; SPATIAL COMPACTORS; TEST RESPONSE COMPACTION; TIME COMPACTORS; UNKNOWN STATES;

EMBEDDED SYSTEMS;

EID: 16444384028     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.844111     Document Type: Article

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