SSMCB: Low-power variation-tolerant source-synchronous multicycle bus

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 2, 2009, Pages 384-394

  Ghoneima, Maged ^a   Ismail, Yehea ^b   Khellah, Muhammad ^c   De, Vivek ^c  

^a NVIDIA   (United States)

^b Northwestern University   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Buses; Coupling capacitance; Interconnects; Jitter; Networks on chip; Source synchronous

Indexed keywords

BUSES; CIRCUIT SIMULATION; CLOCKS; ENERGY CONSERVATION; INTEGRATED CIRCUIT INTERCONNECTS; JITTER; MONTE CARLO METHODS; NETWORK-ON-CHIP; OPTICAL INTERCONNECTS;

CAPACITIVE COUPLINGS; COUPLING CAPACITANCE; INTERCONNECT SCHEMES; NETWORKS ON CHIPS; PERFORMANCE DEGRADATION; PROCESS ENVIRONMENT; SOURCE SYNCHRONOUS; SYNCHRONIZATION SCHEME;

FLIP FLOP CIRCUITS;

EID: 61349199093     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2001805     Document Type: Article

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