Low-K interconnect stack with thick metal 9 redistribution layer and Cu die bump for 45nm high volume manufacturing

2008 IEEE International Interconnect Technology Conference, IITC

Volumn , Issue , 2008, Pages 216-218

  Ingerly, D ^a   Agraharam, S ^a   Becher, D ^a   Chikarmane, V ^a   Fischer, K ^a   Grover, R ^a   Goodner, M ^a   Haight, S ^a   He, J ^a   Ibrahim, T ^a   Joshi, S ^a   Kothari, H ^a   Lee, K ^a   Lin, Y ^a   Litteken, C ^a   Liu, H ^a   Mays, E ^a   Moon, P ^a   Mule', T ^a   Nolen, S ^a   Patel, N ^a   Pradhan, S ^a   Robinson, J ^a   Ramanarayanan, P ^a   Sattiraju, S ^a   Schroeder, T ^a   Williams, S ^a   Yashar, P ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; COPPER; LEAD;

AGGRESSIVE SCALING; HIGH-PERFORMANCE LOGIC; INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE; LOW-K DIELECTRICS;

METALS;

EID: 50949133842     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2008.4546971     Document Type: Conference Paper

References (7)

1. K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning and 100% Pb-free Packaging," IEDM Tech. Dig., pp. 247-250, 2007.
2. J. Cannis, "Green IC Packaging," Advanced Packaging, vol. 8, pp 33-38, 2001.
3. P. Bai et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-K ILD, and .57um SRAM Cell," IEDM Tech Dig, pp 657-60, 2004.
4. A Yeoh et al, "Copper Die Bumps (first level Interconnect) and Low-K Dielectric in 65nm High Volume Manufacturing," ECTC Proceeding 2006.
5. "Temperature Cycling," JESD22-A104-C, May 2005.
6. "Accelerated Moisture Resistance - unbiased HAST," JESD22-A118, December 2000.
7. "Highly Accelerated Temperature and Humidity Stress (HAST)," JESD22-A110-B, February 1999.