Scalable and reliable communication for hardware transactional memory

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2008, Pages 144-154

  Pugsley, Seth H ^a   Awasthi, Manu ^a   Madan, Niti ^a   Muralimanohar, Naveen ^a   Balasubramonian, Rajeev ^a  

^a University of Utah   (United States)

Author keywords

Algorithms for Transaction Commit; Handling Message Loss; Hardware Transactional Memory; On Chip Network Messages; Reliability; Token Coherence

Indexed keywords

CACHE COHERENCES; CONFLICT DETECTIONS; DISTRIBUTED MEMORY SYSTEMS; HANDLING MESSAGE LOSS; IN NETWORKS; MULTI-THREADED PROGRAMS; MULTIPLE TRANSACTIONS; NOVEL ALGORITHMS; ON-CHIP NETWORK MESSAGES; PERFORMANCE IMPROVEMENTS; RELIABLE COMMUNICATIONS; SMALL GROUPS; SYNTHETIC WORKLOADS; TOKEN COHERENCE; VERSIONING;

ARTS COMPUTING; DECODING; ELECTRIC NETWORK TOPOLOGY; PARALLEL ARCHITECTURES; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION NETWORKS;

ALGORITHMS;

EID: 63549087228     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1454115.1454137     Document Type: Conference Paper

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