Bulk disambiguation of speculative threads in multiprocessors

Proceedings - International Symposium on Computer Architecture

Volumn 2006, Issue , 2006, Pages 227-238

  Ceze, Luis ^a   Tuck, James ^a   Caşcaval, Cǎlin ^b   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHECKPOINTED MULTIPROCESSORS; DATA DEPENDENCES; THREAD LEVEL SPECULATION (TLS); TRANSACTIONAL MEMORY (TM);

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA REDUCTION; ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS; INFORMATION ANALYSIS;

MULTIPROCESSING SYSTEMS;

EID: 33845866604     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2006.13     Document Type: Conference Paper

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