Removing architectural bottlenecks to the scalability of speculative parallelization

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2001, Pages 204-215

  Prvulovic, Milos ^a   Garzarén, María ^a   Rauchwerger, Lawrence ^b   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); NETWORK PROTOCOLS; SEMANTICS; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION TRAFFIC;

SCALABILITY; SPECULATIVE BUFFER OVERFLOW; SPECULATIVE PARALLELIZATION;

PARALLEL PROCESSING SYSTEMS;

EID: 0034852757     PISSN: 08847495     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCA.2001.937450     Document Type: Article

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