Estimation of the likelihood of capacitive coupling noise

Proceedings-Design Automation Conference

Volumn , Issue , 2002, Pages 653-658

  Vrudhula, Sarma B K ^a   Blaauw, David ^b,d   Sirichotiyakul, Supamas ^c,d  

^a UNIVERSITY OF ARIZONA   (United States)

^b The Department of Civil and Environmental Engineering   (United States)

^c SUN MICROSYSTEMS   (United States)

^d MOTOROLA INC   (United States)

Author keywords

Deep Submicron; Noise; Signal Integrity

Indexed keywords

CAPACITIVE COUPLING NOISE;

ESTIMATION; INDUCTANCE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROBABILITY DISTRIBUTIONS; RANDOM PROCESSES; RELIABILITY;

SPURIOUS SIGNAL NOISE;

EID: 0036044638     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012706     Document Type: Article

References (17)

1. TACO: Timing analysis with coupling
2. New approaches to noise-aware static timing analysis
3. Towards true crosstalk noise analysis
4. Improved crosstalk modeling for noise constrained interconnect optimization
5. Efficient coupled noise estimation for on-chip interconnects
6. On-chip inductance modeling and analysis
7. False-noise analysis using logic implications
8. Circuit-aware on-chip inductance extraction
9. Switch factor based analysis of coupled RC interconnects
10. ClariNet: A noise analysis tool for deep submicron design
11. On the chicken-and-egg problem of determining the effect of crosstalk on delay in integrated circuits
12. Crosstalk delay analysis using relative window method
13. Noise in deep submicron digital design
14. Driver modeling and alignment of worst-case delay noise
15. Getting to the bottom of deep submicron
16. Crosstalk in VLSI interconnections