A methodology for constraint-driven synthesis of on-chip communications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 3, 2009, Pages 364-377

  Pinto, Alessandro ^a   Carloni, Luca P ^b   Sangiovanni Vincentelli, Alberto L ^c  

^a UNITED TECHNOLOGIES RESEARCH CENTER   (United States)

^b Department of Earth and Environmental Sciences   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Communication synthesis; Interconnect synthesis; Performance optimization; System on chip (SoC)

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS;

AS INTERFACES; COMMUNICATION SYNTHESIS; COMPOSITION RULES; INTERCONNECT SYNTHESIS; LEVELS OF ABSTRACTIONS; MATHEMATICAL FRAMEWORKS; ON-CHIP COMMUNICATIONS; OPTIMIZATION FRAMEWORKS; PERFORMANCE OPTIMIZATION; SYSTEM-ON-CHIP (SOC);

COMMUNICATION;

EID: 60749096629     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2013273     Document Type: Article

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