Replacing global wires with an on-chip network: A power analysis

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 369-374

  Heo, Seongmoo ^a   Asanović, Krste ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

On Chip Network Power Model; Pipelining; Router; Tile Size; Tiled Architecture; Wire Power Model

Indexed keywords

ELECTRIC WIRE; OPTIMIZATION; POWER ELECTRONICS; ROUTERS; SIGNAL ENCODING; SWITCHING CIRCUITS; VOLTAGE CONTROL;

ON-CHIP NETWORK POWER MODEL; PIPELINING; TILE SIZE; TILED ARCHITECTURE;

MICROPROCESSOR CHIPS;

EID: 28444486983     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195549     Document Type: Conference Paper

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