Methodology for correct-by-construction latency insensitive design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 309-315

  Carloni, Luca P ^a   McMillan, Kenneth L ^a   Saldanha, Alexander ^a   Sangiovanni Vincentelli, Alberto L ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONSTRAINT THEORY; ELECTRIC WIRE; FLIP FLOP CIRCUITS; INTELLECTUAL PROPERTY; MICROCOMPUTERS; NETWORK PROTOCOLS;

CLOCK CYCLE CONSTRAINT; DEEP SUBMICRON DESIGN; LATENCY INSENSITIVE DESIGN;

COMPUTER AIDED DESIGN;

EID: 0033334449     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)