Coping with latency in SOC design

IEEE Micro

Volumn 22, Issue 5, 2002, Pages 24-35

  Carloni, Luca P ^a   Sangiovanni Vincentelli, Alberto L ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0036761284     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2002.1044297     Document Type: Review

References (6)

1. K. Keutzer et al., "System Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, Dec. 2000, pp. 1523-1543.
2. P. Glaskowski, "Pentium 4 (Partially) Previewed," Microprocessor Report, vol. 14, no. 8, Aug. 2000, pp. 10-13.
3. L.P. Carloni, K.L. McMillan, and A.L. Sangiovanni-Vincentelli, "Theory of Latency-Insensitive Design," IEEE Trans. Computer-Aided Design, vol. 20, no. 9, Sept. 2001, pp. 1059-1076.
4. L.P. Carloni et al., "A Methodology for 'Correct-by-Construction' Latency Insensitive Design," Proc. Int'l Conf. Computer-Aided Design (ICCAD 99), IEEE Press, Piscataway, N.J., 1999, pp. 309-315.
5. T. Chelcea and S. Novick, "Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, New York, 2001, pp. 21-26.
6. L.P. Carloni and A.L. Sangiovanni-Vincentelli, "Performance Analysis and Optimization of Latency Insensitive Systems," Proc. 37th Design Automation Conf. (DAC 00), IEEE Press, Piscataway, N.J., 2000, pp. 361-367.