Application specific network-on-chip design with guaranteed quality approximation algorithms

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 184-190

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a   Konjevod, Goran ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC NETWORK; APPLICATION-SPECIFIC; BENCHMARK APPLICATIONS; COMMUNICATION PERFORMANCES; DESIGN AUTOMATION CONFERENCE (DAC); FLOOR PLANNING; GUARANTEED QUALITY; HEURISTIC TECHNIQUES; INTEGER LINEAR PROGRAMMING (ILP); MULTI PROCESSOR SYSTEM ON CHIP (MP SOC); NETWORK-ON-CHIP (NOC); NOC ARCHITECTURES; NOC DESIGN; PERFORMANCE REQUIREMENTS; POWER CONSUMPTION (CE); ROUTE GENERATION; SOUTH PACIFIC; SYSTEM LEVELS; TOPOLOGY GENERATION; TWO STAGES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPROXIMATION ALGORITHMS; APPROXIMATION THEORY; ARCHITECTURE; AUTOMATION; BENCHMARKING; COMMUNICATION; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; CONFORMAL MAPPING; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; HEURISTIC METHODS; HEURISTIC PROGRAMMING; INDUSTRIAL ENGINEERING; INTEGER PROGRAMMING; INTEGRATED CIRCUITS; LINEAR PROGRAMMING; LINEARIZATION; MECHANIZATION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; OPTIMIZATION; POLYNOMIAL APPROXIMATION; ROUTERS; ROUTING ALGORITHMS; STAGES; TOPOLOGY;

ARCHITECTURAL DESIGN;

EID: 46649116535     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.357983     Document Type: Conference Paper

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