-
1
-
-
18144415503
-
Systematic Defects in Deep Sub-Micron Technologies
-
Oct
-
B. Kruseman, A. Majhi, C. Hora, S. Eichenberger, and J. Meirlevede, "Systematic Defects in Deep Sub-Micron Technologies", in Proc. Int. Test Conf., Oct. 2004, pp. 290-299.
-
(2004)
Proc. Int. Test Conf
, pp. 290-299
-
-
Kruseman, B.1
Majhi, A.2
Hora, C.3
Eichenberger, S.4
Meirlevede, J.5
-
2
-
-
18144367789
-
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions
-
Oct
-
P. Nigh and A. Gattiker, "Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions", in Proc. Int. Test Conf., Oct. 2004, pp. 309-318.
-
(2004)
Proc. Int. Test Conf
, pp. 309-318
-
-
Nigh, P.1
Gattiker, A.2
-
3
-
-
18144380741
-
In Search of the Optimum. Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost
-
Oct
-
R. Madge, B. Benware, R. Turakhia, R. Daasch, C. Schuermyer, and J. Ruffler, "In Search of the Optimum. Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost", in Proc. Int. Test Conf, Oct. 2004, pp. 203-212.
-
(2004)
Proc. Int. Test Conf
, pp. 203-212
-
-
Madge, R.1
Benware, B.2
Turakhia, R.3
Daasch, R.4
Schuermyer, C.5
Ruffler, J.6
-
4
-
-
14844366560
-
Data Mining Integrated Circuit Fails with Fail Commonalities
-
Oct
-
L. M. Huisman, M. Kassab, and L. Pastel, "Data Mining Integrated Circuit Fails with Fail Commonalities", in Proc. Int. Test Conf., Oct. 2004, pp. 661-668.
-
(2004)
Proc. Int. Test Conf
, pp. 661-668
-
-
Huisman, L.M.1
Kassab, M.2
Pastel, L.3
-
5
-
-
0034482031
-
Stuck-Fault Tests vs. Actual Defects
-
Oct
-
E. J. McCluskey and C. W. Tseng, "Stuck-Fault Tests vs. Actual Defects", in Proc. Int. Test Conf., Oct. 2000, pp. 336-343.
-
(2000)
Proc. Int. Test Conf
, pp. 336-343
-
-
McCluskey, E.J.1
Tseng, C.W.2
-
6
-
-
0142184765
-
Analyzing the Effectiveness of Multiple-Detect Test Set
-
Oct
-
R. D. Blanton, K. N. Dwaarakanth, and A. B. Shah, "Analyzing the Effectiveness of Multiple-Detect Test Set", in Proc. Int. Test Conf., Oct. 2003, pp. 876-885.
-
(2003)
Proc. Int. Test Conf
, pp. 876-885
-
-
Blanton, R.D.1
Dwaarakanth, K.N.2
Shah, A.B.3
-
7
-
-
3142752873
-
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
-
Apr
-
S. Venkataraman, S. Sivaraj, E. Amyeen, S. Lee, A. Ojha, and R. Guo, "An Experimental Study of N-Detect Scan ATPG Patterns on a Processor", in Proc. VLSI Test Symposium, Apr. 2004, pp. 23-28.
-
(2004)
Proc. VLSI Test Symposium
, pp. 23-28
-
-
Venkataraman, S.1
Sivaraj, S.2
Amyeen, E.3
Lee, S.4
Ojha, A.5
Guo, R.6
-
8
-
-
33847097155
-
Gate Exhaustive Testing
-
Nov
-
K. Y. Cho, S. Mitra, and E. J. McCIuskey, "Gate Exhaustive Testing", in Proc. Int. Test Conf., Nov. 2005, pp. 771-777.
-
(2005)
Proc. Int. Test Conf
, pp. 771-777
-
-
Cho, K.Y.1
Mitra, S.2
McCIuskey, E.J.3
-
9
-
-
0034482034
-
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
-
Oct
-
S. T. Zachariah and S. Chakravarty, "A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits", in Proc. Int. Test Conf, Oct. 2000, pp. 750-759.
-
(2000)
Proc. Int. Test Conf
, pp. 750-759
-
-
Zachariah, S.T.1
Chakravarty, S.2
-
10
-
-
84886493185
-
-
S. Chakravarty, et al., Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor, in Proc. VLSI Test Symposium, May 2005, pp. 337-342.
-
S. Chakravarty, et al., "Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor", in Proc. VLSI Test Symposium, May 2005, pp. 337-342.
-
-
-
-
11
-
-
0024124693
-
Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis
-
Sep
-
F. J. Ferguson and J. P. Shen, "Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis", in Proc. Int. Test Conf., Sep. 1988, pp. 475-484.
-
(1988)
Proc. Int. Test Conf
, pp. 475-484
-
-
Ferguson, F.J.1
Shen, J.P.2
-
12
-
-
0032024307
-
Diagnosing Realistic Bridging Faults with Single Stuck-at Information
-
D. B. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson, "Diagnosing Realistic Bridging Faults with Single Stuck-at Information", IEEE Trans. Computer-Aided Design, Vol. 17, No. 3, 1998, pp. 255-268.
-
(1998)
IEEE Trans. Computer-Aided Design
, vol.17
, Issue.3
, pp. 255-268
-
-
Lavo, D.B.1
Chess, B.2
Larrabee, T.3
Ferguson, F.J.4
-
13
-
-
0029510949
-
An Experimental Chip to Evaluate Test Techniques Experimental Results
-
Oct
-
S. C. Ma, P. Franco, and E. J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experimental Results", in Proc. Int. Test Conf., Oct. 1995, pp. 663-672.
-
(1995)
Proc. Int. Test Conf
, pp. 663-672
-
-
Ma, S.C.1
Franco, P.2
McCluskey, E.J.3
-
14
-
-
0027555924
-
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
-
P. Maxwell and R. Aitken, 'Test Sets and Reject Rates: All Fault Coverages are Not Created Equal", IEEE Design and Test of Computers, Vol. 10, No. 1, 1993, pp. 42-51.
-
(1993)
IEEE Design and Test of Computers
, vol.10
, Issue.1
, pp. 42-51
-
-
Maxwell, P.1
Aitken, R.2
-
15
-
-
0034476391
-
Test Method Evaluation Experiments and Data
-
Oct
-
P. Nigh and A. Gatnker, 'Test Method Evaluation Experiments and Data", in Proc. Int. Test Conf., Oct. 2000, pp. 454-463.
-
(2000)
Proc. Int. Test Conf
, pp. 454-463
-
-
Nigh, P.1
Gatnker, A.2
-
16
-
-
0027646703
-
Scan-based Transition Test
-
Aug
-
J. Savir and S. Paul, "Scan-based Transition Test", IEEE Trans. Computer-Aided Design, Vol. 12, No.8, Aug 1993, pp. 1232-1241.
-
(1993)
IEEE Trans. Computer-Aided Design
, vol.12
, Issue.8
, pp. 1232-1241
-
-
Savir, J.1
Paul, S.2
-
17
-
-
84886571398
-
-
Y.-S. Chang, S. Chakravarty, H. Hoang, N. Thorpe, and K. Wee, 'Transition Tests for High Performance Microprocessors, in Proc. VLSI Test Symposium, May 2005, pp. 29-34.
-
Y.-S. Chang, S. Chakravarty, H. Hoang, N. Thorpe, and K. Wee, 'Transition Tests for High Performance Microprocessors", in Proc. VLSI Test Symposium, May 2005, pp. 29-34.
-
-
-
-
18
-
-
0022307908
-
Model for Delay Faults Based on Paths
-
Nov
-
G. L. Smith, "Model for Delay Faults Based on Paths", in Proc. Int. Test Conf., Nov. 1985, pp. 342-349.
-
(1985)
Proc. Int. Test Conf
, pp. 342-349
-
-
Smith, G.L.1
-
19
-
-
21644442215
-
Transient Current Testing of Dynamic CMOS Circuits in the Presence of Leakage and Process Variation
-
Dec
-
A. Chehab, A. Kayssi, A. Nazer, and N. Aaraj, "Transient Current Testing of Dynamic CMOS Circuits in the Presence of Leakage and Process Variation", in Proc. Int. Conf. on Microelectronics, Dec. 2004, pp. 381-387.
-
(2004)
Proc. Int. Conf. on Microelectronics
, pp. 381-387
-
-
Chehab, A.1
Kayssi, A.2
Nazer, A.3
Aaraj, N.4
-
20
-
-
39749142615
-
Modeling and Testing Process Variation in Nanometer CMOS
-
Oct
-
M. Nourani and A. Radhakrishnan, "Modeling and Testing Process Variation in Nanometer CMOS", in Proc. Int. Test Conf., Oct. 2006, pp. 1-10.
-
(2006)
Proc. Int. Test Conf
, pp. 1-10
-
-
Nourani, M.1
Radhakrishnan, A.2
-
21
-
-
0029718603
-
A Diagnosability Metric for Parametric Path Delay Faults
-
Apr
-
M. Sivaraman and A. J. Strojwas, "A Diagnosability Metric for Parametric Path Delay Faults", in Proc. VLSI Test Symposium, Apr. 1996, pp. 316-322.
-
(1996)
Proc. VLSI Test Symposium
, pp. 316-322
-
-
Sivaraman, M.1
Strojwas, A.J.2
-
22
-
-
0142246882
-
Deformations of IC Structure in Test and Yield Learning
-
Oct
-
W. Mally, A Gattiker, T. Zanon, T. Vogels, R. D. Blanton, and T. Storey, "Deformations of IC Structure in Test and Yield Learning", in Proc. Int. Test Conf, Oct. 2003, pp. 856-865.
-
(2003)
Proc. Int. Test Conf
, pp. 856-865
-
-
Mally, W.1
Gattiker, A.2
Zanon, T.3
Vogels, T.4
Blanton, R.D.5
Storey, T.6
-
23
-
-
39749145912
-
Testing for Systematic Defects Based on DFM Guidelines
-
Oct
-
D. Kim, M. E. Amyeen, S. Venkataraman, I. Pomeranz, S. Basumallick, and B. Landau, "Testing for Systematic Defects Based on DFM Guidelines", in Proc. Int. Test Conf., Oct. 2007, pp. 1-10.
-
(2007)
Proc. Int. Test Conf
, pp. 1-10
-
-
Kim, D.1
Amyeen, M.E.2
Venkataraman, S.3
Pomeranz, I.4
Basumallick, S.5
Landau, B.6
-
24
-
-
0025416339
-
Physical Design of Testable VLSI:Techniques and Experiments
-
Apr
-
M. E. Levitt and J. A. Abraham, "Physical Design of Testable VLSI:Techniques and Experiments", IEEE Journal of Solid-state Circuits, vol. 25, Apr. 1990, pp. 474-481.
-
(1990)
IEEE Journal of Solid-state Circuits
, vol.25
, pp. 474-481
-
-
Levitt, M.E.1
Abraham, J.A.2
-
25
-
-
33845333358
-
Defect-oriented Test and Layout Generation for Standard-cell ASIC Designs
-
Sep
-
J. Sudbrock, et al., "Defect-oriented Test and Layout Generation for Standard-cell ASIC Designs", in Euromicro Conference on Digital System Design, Sep. 2005, pp. 79-82.
-
(2005)
Euromicro Conference on Digital System Design
, pp. 79-82
-
-
Sudbrock, J.1
-
26
-
-
0032645516
-
A Systematic DFT Procedure for Library Cells
-
Apr
-
J. Xu, R. Kundu, and E. J. Ferguson, "A Systematic DFT Procedure for Library Cells", in Proc. VLSI Test Symposium, Apr. 1999, pp. 460-466.
-
(1999)
Proc. VLSI Test Symposium
, pp. 460-466
-
-
Xu, J.1
Kundu, R.2
Ferguson, E.J.3
-
27
-
-
49749085853
-
Automated Testability Enhancements for Logic Brick Libraries
-
Mar
-
J. G. Brown, B. Taylor, R. D. Blanton, and L. Pileggi, "Automated Testability Enhancements for Logic Brick Libraries", Design Automaton and Test in Europe, Mar. 2008.
-
(2008)
Design Automaton and Test in Europe
-
-
Brown, J.G.1
Taylor, B.2
Blanton, R.D.3
Pileggi, L.4
-
28
-
-
29144501137
-
On Modeling Crosstalk Faults
-
Dec
-
S. Kundu, S. T. Zachariah, Y.-S. Chang, and C. Tirumurti, "On Modeling Crosstalk Faults", IEEE Trans. Computer-Aided Design, Vol. 24, No.12, Dec. 2005, pp. 1909-1915.
-
(2005)
IEEE Trans. Computer-Aided Design
, vol.24
, Issue.12
, pp. 1909-1915
-
-
Kundu, S.1
Zachariah, S.T.2
Chang, Y.-S.3
Tirumurti, C.4
-
29
-
-
0343826160
-
RT-level ITC'99 Benchmarks and First ATPG Results
-
Jul.-Sep
-
F. Como, M. S. Reorda, and G Squillero, "RT-level ITC'99 Benchmarks and First ATPG Results", IEEE Design and Test of Computers, Jul.-Sep. 2000, pp. 44-53.
-
(2000)
IEEE Design and Test of Computers
, pp. 44-53
-
-
Como, F.1
Reorda, M.S.2
Squillero, G.3
-
30
-
-
33746163470
-
A Framework for High-Level Synthesis of System-on-Chip Designs
-
Jun
-
J. E. Stine, J. Grad, I. Castellanos, J. Blank, V. Dave, M. Prakash, N. Iliev, and N. Jachimiec, "A Framework for High-Level Synthesis of System-on-Chip Designs", in Proc. Int. Conf. on Microelectronic Systems Education, Jun. 2005, pp. 67-68.
-
(2005)
Proc. Int. Conf. on Microelectronic Systems Education
, pp. 67-68
-
-
Stine, J.E.1
Grad, J.2
Castellanos, I.3
Blank, J.4
Dave, V.5
Prakash, M.6
Iliev, N.7
Jachimiec, N.8
-
31
-
-
58249096704
-
-
Cadence Design Systems, Jun
-
"Diva® Reference", Cadence Design Systems, Jun. 2005.
-
(2005)
Diva® Reference
-
-
-
32
-
-
33751110266
-
-
H. Lee, I. Pomeranz, and S. M. Reddy, A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults, in Proc. VLSI Test Symposium, May 2006, pp. 294-299.
-
H. Lee, I. Pomeranz, and S. M. Reddy, "A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults", in Proc. VLSI Test Symposium, May 2006, pp. 294-299.
-
-
-
-
33
-
-
0031680074
-
MIX : A Test Generation System for Synchronous Sequential Circuits
-
Jan
-
X. Lin, I. Pomeranz, and S. M. Reddy, "MIX : A Test Generation System for Synchronous Sequential Circuits", in Proc. Int. Conf. on VLSI Design, Jan. 1998, pp.456-463.
-
(1998)
Proc. Int. Conf. on VLSI Design
, pp. 456-463
-
-
Lin, X.1
Pomeranz, I.2
Reddy, S.M.3
|