An experimental study of N-detect scan ATPG patterns on a processor

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2004, Pages 23-28

  Venkataraman, Srikanth ^a   Sivaraj, Srihari ^a   Amyeen, Enamul ^a   Lee, Sangbong ^a   Ojha, Ajay ^a   Guo, Ruifeng ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT MODELS; INTEL (CO); STUCK-AT FAULT MODELS; TEST COSTS;

COMPUTER SIMULATION; COSTS; DESIGN FOR TESTABILITY; ERRORS; MICROPROCESSOR CHIPS; OPTIMIZATION; PROBABILITY; PROGRAM PROCESSORS; QUALITY CONTROL; TEST FACILITIES;

ELECTRON DEVICE TESTING;

EID: 3142752873     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2004.1299221     Document Type: Conference Paper

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