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Volumn , Issue , 2006, Pages
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Modeling and testing process variation in nanometer CMOS
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Author keywords
[No Author keywords available]
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Indexed keywords
DIGITAL SIGNAL PROCESSING;
FAILURE ANALYSIS;
FREQUENCY DOMAIN ANALYSIS;
NETWORKS (CIRCUITS);
PARAMETER ESTIMATION;
SPURIOUS SIGNAL NOISE;
DEVICE TECHNOLOGY;
FREQUENCYSENSITIVE CIRCUITS;
TESTING PROCESS;
CMOS INTEGRATED CIRCUITS;
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EID: 39749142615
PISSN: 10893539
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/TEST.2006.297716 Document Type: Conference Paper |
Times cited : (6)
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References (31)
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