RT-level ITC'99 benchmarks and first ATPG results

IEEE Design and Test of Computers

Volumn 17, Issue 3, 2000, Pages 44-52

  Corno, Fulvio ^b   Reorda, Matteo Sonza ^b   Squillero, Giovanni ^a  

^a POLITECNICO DI TORINO   (Italy)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; BENCHMARKING; COMPUTER AIDED LOGIC DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DESIGN FOR TESTABILITY; ELECTRONIC DATA INTERCHANGE; FLIP FLOP CIRCUITS; LOGIC GATES; PROGRAM COMPILERS; SHIFT REGISTERS;

AUTOMATIC TEST PATTERN GENERATOR; BENCHMARK CIRCUITS; CENTRAL PROCESSING UNIT; REGISTER TRANSFER LEVEL; TEST TOOLS;

COMPUTER TESTING;

EID: 0343826160     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.867894     Document Type: Article

References (16)

1. F. Brglez, and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran", Proc. IEEE Int'l Symp. Circuits and Systems, IEEE Computer Soc. Press, Los Alamitos, Calif., June 1985, pp. 695-698.
2. F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l. Symp. Circuits and Systems, IEEE Computer Soc. Press, Los Alamitos, Calif., 1989, pp. 1929-1934.
3. "High Time for High-Level Test Generation," Panel at ITC99: Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1999, pp. 1112-1119.
4. M.B. Santos, et al, "RTL-based Functional Test Generation For High Defect Coverage in Digital SoCs," IEEE European Test Workshop, Cascais (P), IEEE Computer Soc. Press, Los Alamitos, Calif., May 2000, pp. 99-104.
5. "ITC'99 Benchmark Circuits?Preliminary Results," Panel at ITC'99: Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1999, pp. 1125-1130.
6. F. Corno, P. Prinetto, and M. Sonza Reorda, "Testability analysis and ATPG on behavioral RT-level VHDL," Proc. IEEE Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1997, pp. 753-759.
7. F. Corno, et al, "Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience," IEEE Design, Automation and Test in Europe, Paris (F), IEEE Computer Soc. Press, Los Alamitos, Calif., March 2000, pp. 385-389.
8. Politecnico di Torino ITC'99 benchkmarks, downloadable at the URL http://www.cad.polito.it/tools/itc99.html.
9. F. Corno, M. Sonza Reorda, and G. Squillero, "High-Level Observability for Effective High-Level ATPG, VTS-2000," 18th IEEE VLSI Test Symp., Montreal (CA), IEEE Computer Soc. Press, Los Alamitos, Calif., May 2000, pp. 411-416
10. D. Moundanos, J.A. Abraham, and Y.V. Hoskote, "A Unified Framework for Design Validation and Manifacturing Test," Proc. IEEE Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1996, pp. 875-884.
11. K.-T. Cheng, and A.S. Khrishnakumar, "Automatic Generation of Functional Vectors Using the Extended Finite State Machine Model," ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, Jan. 1996, pp. 57-79.
12. F. Ferrandi, F. Fummi, and D. Sciuto, "Implicit Test Generation for Behavioral VHDL Models," Proc. IEEE Int'l. Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1998, pp. 436-441.
13. F. Fallah, P. Ashar, and S. Devadas, "Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage," Proc. 35th Design Automation Conf., ACM press, 1999, pp. 666-671.
14. S. Devadas, A. Ghosh, and K. Keutzer, "An Observability-Based Code Coverage Metric for Functional Simulation," Proc. IEEE/ACM Int'l Conf. on Computer Aided Design, IEEE Computer Soc. Press, Los Alamitos, Calif., 1996, pp. 418-425.
15. B. Beizer, Software Testing Techniques (second edition), Van Nostrand Rheinold, New York, 1990.
16. P.A. Thaker, V.D. Agrawal, and M.E. Zaghloul, "Validation Vector Grade (VVG): A New Coverage Metric fo Validation and Test," Proc. 15th IEEE VLSI Test Symp., IEEE Computer Soc. Press, Los Alamitos, Calif., 1999, pp. 182-188.