Experimental evaluation of bridge patterns for a high performance microprocessor

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 337-342

  Chakravarty, Sreejit ^a   Chang, Yishing ^a   Hoang, Hiep ^a   Jayaraman, Sridhar ^a   Picano, Silvio ^a   Prunty, Cheryl ^a   Savage, Eric W ^a   Sheikh, Rehan ^a   Tran, Eric N ^a   Wee, Khen ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGE PATTERNS; DATA POINTS; EXPERIMENTAL EVALUATION; HIGH-PERFORMANCE MICROPROCESSORS; SCAN PATTERNS;

SILICON;

MICROPROCESSOR CHIPS;

EID: 84886493185     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.44     Document Type: Conference Paper

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