Diagnosability metric for parametric path delay faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 316-322

  Sivaraman, Mukund ^a   Strojwas, Andrzej J ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; ERROR DETECTION; ESTIMATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; MATHEMATICAL MODELS; STATISTICAL METHODS; VECTORS;

CHIP FAILURE; DELAY FAULT TESTING; FAULT DIAGNOSABILITY; PARAMETRIC PATH DELAY FAULTS; SENSITIZATION MECHANISM;

INTEGRATED CIRCUIT TESTING;

EID: 0029718603     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)