Testing for systematic defects based on DFM guidelines

Proceedings - International Test Conference

Volumn , Issue , 2007, Pages

  Kim, Dongok ^a   Amyeen, M Enamul ^b   Venkataraman, Srikanth ^b   Pomeranz, Irith ^a   Basumallick, Swagato ^b   Landau, Berni ^b  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FAULT DETECTION; INTEGRATED CIRCUIT LAYOUT; QUALITY CONTROL; TRANSISTORS;

DESIGN-FOR-MANUFACTURING (DFM) LAYOUT; SCHEMATIC LEVEL; SYSTEMATIC DEFECTS;

INTEGRATED CIRCUIT TESTING;

EID: 39749145912     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437603     Document Type: Conference Paper

References (34)