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Volumn , Issue , 2004, Pages 290-299

Systematic defects in deep sub-micron technologies

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DEMODULATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; PROBLEM SOLVING; SIZE DETERMINATION; TOPOLOGY;

EID: 18144415503     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (62)

References (13)
  • 1
    • 33646922057 scopus 로고    scopus 로고
    • The future of wires
    • April
    • R. Ho, K. Mai, and M. Horowitz, "The Future of Wires", Proceedings of the IEEE, Vol. 89., No. 4, pp. 490-504, April 2001.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.4 , pp. 490-504
    • Ho, R.1    Mai, K.2    Horowitz, M.3
  • 2
    • 0036507826 scopus 로고    scopus 로고
    • Maintaining the benefits of CMOS scaling when scaling bogs down
    • March/May
    • E.J. Nowack, "Maintaining the Benefits of CMOS scaling when Scaling Bogs Down", IBM Journal of Research and Development, No. 2/3, March/May 2002.
    • (2002) IBM Journal of Research and Development , Issue.2-3
    • Nowack, E.J.1
  • 3
    • 0025260287 scopus 로고
    • Defect size distributions in very large scale integration chips
    • R. Glang, "Defect size distributions in very large scale integration chips", Proceedings of the IEEE/ICMTS, pp 57-60, 1990
    • (1990) Proceedings of the IEEE/ICMTS , pp. 57-60
    • Glang, R.1
  • 4
    • 0022117706 scopus 로고
    • The role of defect size distribution in yield modeling
    • A. V. Ferris-Prabhu, "The role of defect size distribution in yield modeling", IEEE Trans. Electron Devices, Vol. ED-32, No. 9, pp 1727-1734, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.9 , pp. 1727-1734
    • Ferris-Prabhu, A.V.1
  • 5
    • 18144418526 scopus 로고    scopus 로고
    • What defects escape our tests ... and how will we detect them in the future
    • P. Nigh, "What defects escape our tests ... and how will we detect them in the future", International Test Conference, pp. 1123-1125, 2000
    • (2000) International Test Conference , pp. 1123-1125
    • Nigh, P.1
  • 7
  • 9
    • 0031190581 scopus 로고    scopus 로고
    • Shmoo plotting: The black art of IC testing
    • July-September
    • K. Baker, J. van Beers, "Shmoo Plotting: The Black Art of IC Testing", IEEE Design & Test of Computers, pp. 90-97, July-September 1997.
    • (1997) IEEE Design & Test of Computers , pp. 90-97
    • Baker, K.1    Van Beers, J.2
  • 11
    • 0022201294 scopus 로고
    • Inductive fault analysis of MOS integrated circuits
    • Dec
    • J.P. Shen, W. Maly, F.J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design and Test, Vol.2 2. No. 6. pp. 13-36, Dec 1985.
    • (1985) IEEE Design and Test , vol.22 , Issue.6 , pp. 13-36
    • Shen, J.P.1    Maly, W.2    Ferguson, F.J.3
  • 12
    • 0035004977 scopus 로고    scopus 로고
    • Resistive opens in a class of CMOS latches: Analysis and DFT
    • A. Zenteno, V. Champac, "Resistive Opens in a Class of CMOS Latches: Analysis and DFT", VLSI Test Symposium, pp. 138-144, 2001.
    • (2001) VLSI Test Symposium , pp. 138-144
    • Zenteno, A.1    Champac, V.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.