On the minimization of potential transient errors and SER in logic circuits using SPFD

Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

Volumn , Issue , 2008, Pages 123-128

  Almukhaizim, Sobeeh ^a   Makris, Yiorgos ^b   Yang, Yu Shen ^c   Veneris, Andreas ^c  

^a KUWAIT UNIVERSITY   (Kuwait)

^b YALE UNIVERSITY   (United States)

^c UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; ERROR CORRECTION; ERRORS; LARGE SCALE SYSTEMS; LOGIC DESIGN; NETWORKS (CIRCUITS); SWITCHING CIRCUITS; SWITCHING THEORY; WIRE;

BENCHMARK CIRCUITS; DESIGN PARAMETERS; LOGIC SYNTHESIS; ON-LINE TESTING; REPRESENTATION METHOD; SOFT-ERROR RATE; TEST ABILITY; TRANSIENT ERRORS;

LOGIC CIRCUITS;

EID: 52049093860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2008.16     Document Type: Conference Paper

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